424 lines
15 KiB
C
424 lines
15 KiB
C
/**
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******************************************************************************
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* @file stm32c0xx_hal_pwr.c
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* @author MCD Application Team
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* @brief PWR HAL module driver.
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* This file provides firmware functions to manage the following
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* functionalities of the Power Controller (PWR) peripheral:
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* + Initialization/de-initialization functions
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* + Peripheral Control functions
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*
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2022 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "stm32c0xx_hal.h"
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/** @addtogroup STM32C0xx_HAL_Driver
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* @{
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*/
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/** @addtogroup PWR
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* @{
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*/
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#ifdef HAL_PWR_MODULE_ENABLED
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/* Private typedef -----------------------------------------------------------*/
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/* Private define ------------------------------------------------------------*/
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/** @defgroup PWR_Private_Defines PWR Private Defines
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* @{
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*/
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/**
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* @}
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*/
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/* Private macro -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private function prototypes -----------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup PWR_Exported_Functions PWR Exported Functions
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* @{
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*/
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/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
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* @brief Initialization and de-initialization functions
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*
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@verbatim
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===============================================================================
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##### Initialization and de-initialization functions #####
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===============================================================================
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[..]
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@endverbatim
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* @{
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*/
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/**
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* @brief Deinitialize the HAL PWR peripheral registers to their default reset
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values.
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* @retval None
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*/
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void HAL_PWR_DeInit(void)
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{
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__HAL_RCC_PWR_FORCE_RESET();
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__HAL_RCC_PWR_RELEASE_RESET();
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}
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/**
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* @}
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*/
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/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
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* @brief Low Power modes configuration functions
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*
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@verbatim
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===============================================================================
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##### Peripheral Control functions #####
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===============================================================================
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[..]
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*** WakeUp pin configuration ***
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================================
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[..]
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(+) WakeUp pins are used to wakeup the system from Standby mode or
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Shutdown mode. WakeUp pins polarity can be set to configure event
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detection on high level (rising edge) or low level (falling edge).
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*** Low Power mode configuration ***
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=====================================
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[..]
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The devices feature 4 low-power modes:
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(+) Sleep mode: Cortex-M0+ core stopped, peripherals kept running,
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regulator is main mode.
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(+) Stop 0 mode: all clocks are stopped except LSI and LSE, regulator is
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main mode.
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(+) Standby mode: all clocks are stopped except LSI and LSE, regulator is
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disable.
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(+) Shutdown mode: all clocks are stopped except LSE, regulator is
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disable.
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*** Sleep mode ***
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=========================================
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[..]
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(+) Entry:
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The Sleep is entered through HAL_PWR_EnterSLEEPMode() API specifying
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the main regulator per default and if exit is interrupt or event
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triggered.
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(++) PWR_MAINREGULATOR_ON: Sleep mode (regulator in main mode).
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(++) PWR_SLEEPENTRY_WFI: Core enters sleep mode with WFI instruction
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(++) PWR_SLEEPENTRY_WFE: Core enters sleep mode with WFE instruction
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(+) WFI Exit:
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(++) Any interrupt enabled in nested vectored interrupt controller (NVIC)
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(+) WFE Exit:
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(++) Any wakeup event if cortex is configured with SEVONPEND = 0
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(++) Interrupt even when disabled in NVIC if cortex is configured with
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SEVONPEND = 1
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*** Stop 0 mode ***
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=============================
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[..]
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(+) Entry:
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The Stop modes are entered through the following APIs:
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(++) HAL_PWR_EnterSTOPMode() with following settings:
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(+++) PWR_MAINREGULATOR_ON to enter STOP0 mode.
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(+) Exit (interrupt or event-triggered, specified when entering STOP mode):
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(++) PWR_STOPENTRY_WFI: enter Stop mode with WFI instruction
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(++) PWR_STOPENTRY_WFE: enter Stop mode with WFE instruction
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(+) WFI Exit:
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(++) Any EXTI line (internal or external) configured in interrupt mode
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with corresponding interrupt enable in NVIC
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(+) WFE Exit:
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(++) Any EXTI line (internal or external) configured in event mode if
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cortex is configured with SEVONPEND = 0
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(++) Any EXTI line configured in interrupt mode (even if the
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corresponding EXTI Interrupt vector is disabled in the NVIC) if
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cortex is configured with SEVONPEND = 0. The interrupt source can
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be external interrupts or peripherals with wakeup capability.
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*** Standby mode ***
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====================
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[..]
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(+) Entry:
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(++) The Standby mode is entered through HAL_PWR_EnterSTANDBYMode() API, by
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setting SLEEPDEEP in Cortex control register.
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(+) Exit:
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(++) WKUP pin edge detection, RTC event (alarm, timestamp),
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LSE CSS detection, reset on NRST pin, IWDG reset & BOR reset.
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[..] Exiting Standby generates a power reset: Cortex is reset and execute
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Reset handler vector, all registers in the Vcore domain are set to
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their reset value. Registers outside the VCORE domain (RTC, WKUP, IWDG,
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and Standby/Shutdown modes control) are not impacted.
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*** Shutdown mode ***
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======================
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[..]
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In Shutdown mode,
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voltage regulator is disabled, all clocks are off except LSE, RRS bit is
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cleared. SRAM and registers contents are lost except for backup domain
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registers.
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(+) Entry:
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(++) The Shutdown mode is entered through HAL_PWREx_EnterSHUTDOWNMode() API,
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by setting SLEEPDEEP in Cortex control register.
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(+) Exit:
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(++) WKUP pin edge detection, RTC event (alarm, timestamp),
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LSE CSS detection, reset on NRST pin.
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[..] Exiting Shutdown generates a brown out reset: Cortex is reset and execute
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Reset handler vector, all registers are set to their reset value but ones
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in backup domain.
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@endverbatim
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* @{
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*/
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/**
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* @brief Enable the WakeUp PINx functionality.
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* @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.
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* This parameter can be one of the following legacy values which set
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* the default polarity i.e. detection on high level (rising edge):
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* @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
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* PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 (Only on STM32C071xx), PWR_WAKEUP_PIN6
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* or one of the following value where the user can explicitly specify
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* the enabled pin and the chosen polarity:
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* @arg @ref PWR_WAKEUP_PIN1_HIGH or PWR_WAKEUP_PIN1_LOW
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* @arg @ref PWR_WAKEUP_PIN2_HIGH or PWR_WAKEUP_PIN2_LOW
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* @arg @ref PWR_WAKEUP_PIN3_HIGH or PWR_WAKEUP_PIN3_LOW
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* @arg @ref PWR_WAKEUP_PIN4_HIGH or PWR_WAKEUP_PIN4_LOW
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* @arg @ref PWR_WAKEUP_PIN5_HIGH or PWR_WAKEUP_PIN5_LOW (*)
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* @arg @ref PWR_WAKEUP_PIN6_HIGH or PWR_WAKEUP_PIN6_LOW
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* @note PWR_WAKEUP_PINx and PWR_WAKEUP_PINx_HIGH are equivalent.
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* @note (*) Availability depends on devices
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* @retval None
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*/
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void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinPolarity)
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{
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assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinPolarity));
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/* Specifies the Wake-Up pin polarity for the event detection
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(rising or falling edge) */
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MODIFY_REG(PWR->CR4, (PWR_CR4_WP & WakeUpPinPolarity), (WakeUpPinPolarity >> PWR_WUP_POLARITY_SHIFT));
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/* Enable wake-up pin */
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SET_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinPolarity));
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}
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/**
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* @brief Disable the WakeUp PINx functionality.
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* @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
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* This parameter can be one of the following values:
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* @arg @ref PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3,
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* PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5 (*), PWR_WAKEUP_PIN6
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* @note (*) Availability depends on devices
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* @retval None
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*/
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void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
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{
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assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
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CLEAR_BIT(PWR->CR3, (PWR_CR3_EWUP & WakeUpPinx));
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}
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/**
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* @brief Enter Sleep mode.
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* @note In Sleep mode, all I/O pins keep the same state as
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* in Run mode.
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* @param Regulator Specifies the regulator state in Sleep mode.
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* This parameter can be the following value:
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* @arg @ref PWR_MAINREGULATOR_ON Sleep mode (regulator in main mode)
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* @param SLEEPEntry Specifies if Sleep mode is entered with WFI or WFE
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* instruction. This parameter can be one of the following values:
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* @arg @ref PWR_SLEEPENTRY_WFI enter Sleep or Low-power Sleep
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* mode with WFI instruction
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* @arg @ref PWR_SLEEPENTRY_WFE enter Sleep or Low-power Sleep
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* mode with WFE instruction
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* @note When WFI entry is used, tick interrupt have to be disabled if not
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* desired as the interrupt wake up source.
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* @retval None
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*/
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void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
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{
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/* Check the parameters */
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assert_param(IS_PWR_REGULATOR(Regulator));
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assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
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/* Clear SLEEPDEEP bit of Cortex System Control Register */
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CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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/* Select SLEEP mode entry -------------------------------------------------*/
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if (SLEEPEntry == PWR_SLEEPENTRY_WFI)
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{
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/* Request Wait For Interrupt */
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__WFI();
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}
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else
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{
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/* Request Wait For Event */
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__SEV();
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__WFE();
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__WFE();
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}
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}
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/**
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* @brief Enter Stop mode
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* @note This API is named HAL_PWR_EnterSTOPMode to ensure compatibility with
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* legacy code running on devices where only "Stop mode" is mentioned
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* with main regulator ON.
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* @note In Stop mode, all I/O pins keep the same state as in Run mode.
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* @note All clocks in the VCORE domain are stopped; the HSI and the
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* HSE oscillators are disabled. Some peripherals with the wakeup
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* capability can switch on the HSI to receive a frame, and switch off
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* the HSI after receiving the frame if it is not a wakeup frame.
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* SRAM and register contents are preserved.
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* @note When exiting Stop 0 mode by issuing an interrupt or a
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* wakeup event, the HSI RC oscillator is selected as system clock
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* @param Regulator Specifies the regulator state in Stop mode
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* This parameter can be of the following value:
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* @arg @ref PWR_MAINREGULATOR_ON Stop 0 mode (main regulator ON)
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* @param STOPEntry Specifies Stop 0 mode is entered with WFI or
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* WFE instruction. This parameter can be one of the following values:
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* @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 mode with WFI
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* instruction.
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* @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 mode with WFE
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* instruction.
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* @retval None
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*/
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void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
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{
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/* Check the parameters */
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assert_param(IS_PWR_REGULATOR(Regulator));
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assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
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MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP0);
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/* Set SLEEPDEEP bit of Cortex System Control Register */
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SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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/* Select Stop mode entry --------------------------------------------------*/
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if (STOPEntry == PWR_STOPENTRY_WFI)
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{
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/* Request Wait For Interrupt */
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__WFI();
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}
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else
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{
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/* Request Wait For Event */
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__SEV();
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__WFE();
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__WFE();
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}
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/* Reset SLEEPDEEP bit of Cortex System Control Register */
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CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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}
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/**
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* @brief Enter Standby mode.
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* @note In Standby mode,the HSI and the HSE oscillators are
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* switched off. SRAM and register contents are lost except
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* for registers in the Backup domain and Standby circuitry.
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* @note The I/Os can be configured either with a pull-up or pull-down or can
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* be kept in analog state.
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* HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown()
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* respectively enable Pull Up and PullDown state.
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* HAL_PWREx_DisableGPIOPullUp() & HAL_PWREx_DisableGPIOPullDown()
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* disable the same. These states are effective in Standby mode only if
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* APC bit is set through HAL_PWREx_EnablePullUpPullDownConfig() API.
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* @retval None
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*/
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void HAL_PWR_EnterSTANDBYMode(void)
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{
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/* Set Stand-by mode */
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MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STANDBY);
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/* Set SLEEPDEEP bit of Cortex System Control Register */
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SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
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/* Request Wait For Interrupt */
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__WFI();
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}
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/**
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* @brief Enable Sleep-On-Exit Cortex feature
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* @note Set SLEEPONEXIT bit of SCR register. When this bit is set, the
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* processor enters SLEEP or DEEPSLEEP mode when an interruption
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* handling is over returning to thread mode. Setting this bit is
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* useful when the processor is expected to run only on interruptions
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* handling.
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* @retval None
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*/
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void HAL_PWR_EnableSleepOnExit(void)
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{
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/* Set SLEEPONEXIT bit of Cortex System Control Register */
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SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
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}
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/**
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* @brief Disable Sleep-On-Exit Cortex feature
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* @note Clear SLEEPONEXIT bit of SCR register. When this bit is set, the
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* processor enters SLEEP or DEEPSLEEP mode when an interruption
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* handling is over.
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* @retval None
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*/
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void HAL_PWR_DisableSleepOnExit(void)
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{
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/* Clear SLEEPONEXIT bit of Cortex System Control Register */
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CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
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}
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/**
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* @brief Enable Cortex Sev On Pending feature.
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* @note Set SEVONPEND bit of SCR register. When this bit is set, enabled
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* events and all interrupts, including disabled ones can wakeup
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* processor from WFE.
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* @retval None
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*/
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void HAL_PWR_EnableSEVOnPend(void)
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{
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/* Set SEVONPEND bit of Cortex System Control Register */
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SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
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}
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/**
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* @brief Disable Cortex Sev On Pending feature.
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* @note Clear SEVONPEND bit of SCR register. When this bit is clear, only
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* enable interrupts or events can wakeup processor from WFE
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* @retval None
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*/
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void HAL_PWR_DisableSEVOnPend(void)
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{
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/* Clear SEVONPEND bit of Cortex System Control Register */
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CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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#endif /* HAL_PWR_MODULE_ENABLED */
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/**
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* @}
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*/
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/**
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* @}
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*/
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