From 84c56e534ea92432160b4552cd3dc0e88c6004fb Mon Sep 17 00:00:00 2001 From: vishnuk-v Date: Tue, 11 Feb 2025 17:53:09 +0530 Subject: [PATCH] incldued the slave present variable to check the neighbouring slave --- .mxproject | 4 +- Core/Inc/stm32c0xx_hal_conf.h | 2 +- Core/Src/main.c | 13 +- Core/Src/stm32c0xx_hal_msp.c | 73 - .../Inc/stm32c0xx_hal_adc.h | 1934 ------ .../Inc/stm32c0xx_hal_adc_ex.h | 185 - .../Inc/stm32c0xx_ll_adc.h | 5516 ----------------- .../Src/stm32c0xx_hal_adc.c | 3066 --------- .../Src/stm32c0xx_hal_adc_ex.c | 417 -- rey_master.ioc | 35 +- 10 files changed, 27 insertions(+), 11218 deletions(-) delete mode 100644 Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h delete mode 100644 Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h delete mode 100644 Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h delete mode 100644 Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c delete mode 100644 Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c diff --git a/.mxproject b/.mxproject index 209bc26..29700b2 100644 --- a/.mxproject +++ b/.mxproject @@ -1,8 +1,8 @@ [PreviousLibFiles] -LibFiles=Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_utils.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_bus.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ramfunc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_dma.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_dmamux.h;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_adc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_adc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_utils.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_bus.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ramfunc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c011xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Source\Templates\system_stm32c0xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSIS\Include\pac_armv81.h;Drivers\CMSIS\Include\pmu_armv8.h;Drivers\CMSIS\Include\tz_context.h; +LibFiles=Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_utils.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_bus.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ramfunc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h;Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_dma.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_dmamux.h;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_system.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_cortex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_rcc_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_rcc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_utils.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_bus.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_flash_ramfunc.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_gpio.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_gpio_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_dma_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_pwr.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_pwr_ex.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_def.h;Drivers\STM32C0xx_HAL_Driver\Inc\Legacy\stm32_hal_legacy.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_ll_exti.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim.h;Drivers\STM32C0xx_HAL_Driver\Inc\stm32c0xx_hal_tim_ex.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c011xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\stm32c0xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Include\system_stm32c0xx.h;Drivers\CMSIS\Device\ST\STM32C0xx\Source\Templates\system_stm32c0xx.c;Drivers\CMSIS\Include\cachel1_armv7.h;Drivers\CMSIS\Include\cmsis_armcc.h;Drivers\CMSIS\Include\cmsis_armclang.h;Drivers\CMSIS\Include\cmsis_armclang_ltm.h;Drivers\CMSIS\Include\cmsis_compiler.h;Drivers\CMSIS\Include\cmsis_gcc.h;Drivers\CMSIS\Include\cmsis_iccarm.h;Drivers\CMSIS\Include\cmsis_version.h;Drivers\CMSIS\Include\core_armv81mml.h;Drivers\CMSIS\Include\core_armv8mbl.h;Drivers\CMSIS\Include\core_armv8mml.h;Drivers\CMSIS\Include\core_cm0.h;Drivers\CMSIS\Include\core_cm0plus.h;Drivers\CMSIS\Include\core_cm1.h;Drivers\CMSIS\Include\core_cm23.h;Drivers\CMSIS\Include\core_cm3.h;Drivers\CMSIS\Include\core_cm33.h;Drivers\CMSIS\Include\core_cm35p.h;Drivers\CMSIS\Include\core_cm4.h;Drivers\CMSIS\Include\core_cm55.h;Drivers\CMSIS\Include\core_cm7.h;Drivers\CMSIS\Include\core_cm85.h;Drivers\CMSIS\Include\core_sc000.h;Drivers\CMSIS\Include\core_sc300.h;Drivers\CMSIS\Include\core_starmc1.h;Drivers\CMSIS\Include\mpu_armv7.h;Drivers\CMSIS\Include\mpu_armv8.h;Drivers\CMSI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[PreviousUsedCubeIDEFiles] -SourceFiles=Core\Src\main.c;Core\Src\stm32c0xx_it.c;Core\Src\stm32c0xx_hal_msp.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32C0xx\Source\Templates\system_stm32c0xx.c;Core\Src\system_stm32c0xx.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_adc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32C0xx\Source\Templates\system_stm32c0xx.c;Core\Src\system_stm32c0xx.c;;; +SourceFiles=Core\Src\main.c;Core\Src\stm32c0xx_it.c;Core\Src\stm32c0xx_hal_msp.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32C0xx\Source\Templates\system_stm32c0xx.c;Core\Src\system_stm32c0xx.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_cortex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_rcc_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_flash_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_gpio.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_dma_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_pwr_ex.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_exti.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim.c;Drivers\STM32C0xx_HAL_Driver\Src\stm32c0xx_hal_tim_ex.c;Drivers\CMSIS\Device\ST\STM32C0xx\Source\Templates\system_stm32c0xx.c;Core\Src\system_stm32c0xx.c;;; HeaderPath=Drivers\STM32C0xx_HAL_Driver\Inc;Drivers\STM32C0xx_HAL_Driver\Inc\Legacy;Drivers\CMSIS\Device\ST\STM32C0xx\Include;Drivers\CMSIS\Include;Core\Inc; CDefines=USE_HAL_DRIVER;STM32C011xx;USE_HAL_DRIVER;USE_HAL_DRIVER; diff --git a/Core/Inc/stm32c0xx_hal_conf.h b/Core/Inc/stm32c0xx_hal_conf.h index 6d2fd4c..9fe13a2 100644 --- a/Core/Inc/stm32c0xx_hal_conf.h +++ b/Core/Inc/stm32c0xx_hal_conf.h @@ -35,7 +35,7 @@ extern "C" { * @brief This is the list of modules to be used in the HAL driver */ #define HAL_MODULE_ENABLED -#define HAL_ADC_MODULE_ENABLED +/* #define HAL_ADC_MODULE_ENABLED */ /* #define HAL_CRC_MODULE_ENABLED */ /* #define HAL_CRYP_MODULE_ENABLED */ /* #define HAL_I2C_MODULE_ENABLED */ diff --git a/Core/Src/main.c b/Core/Src/main.c index a4a68b0..ee89af5 100644 --- a/Core/Src/main.c +++ b/Core/Src/main.c @@ -31,7 +31,16 @@ int main(void) HAL_GPIO_WritePin(GPIOA, Red_LED_OUT_Pin, GPIO_PIN_RESET); // Changed to GPIOA HAL_GPIO_WritePin(GPIOA, LR_OUT_Pin, GPIO_PIN_RESET); HAL_GPIO_WritePin(GPIOA, RL_OUT_Pin, GPIO_PIN_RESET); +// uint8_t slave_present = HAL_GPIO_ReadPin(GPIOA, Slave_Detect_Pin); +// if(slave_present == TRUE) +// { +// HAL_GPIO_WritePin(Last_Node_Switch_GPIO_Port, feed_back_Pin, GPIO_PIN_RESET); +// } +// else +// { +// HAL_GPIO_WritePin(Last_Node_Switch_GPIO_Port, feed_back_Pin, GPIO_PIN_SET); +// } while (1) { @@ -226,8 +235,8 @@ void Error_Handler(void) __disable_irq(); while (1) { - HAL_GPIO_TogglePin(GPIOA, Amber_LED_OUT_Pin | Red_LED_OUT_Pin); - HAL_Delay(500); +// HAL_GPIO_TogglePin(GPIOA, Amber_LED_OUT_Pin | Red_LED_OUT_Pin); +// HAL_Delay(500); } } diff --git a/Core/Src/stm32c0xx_hal_msp.c b/Core/Src/stm32c0xx_hal_msp.c index de90b09..3202d62 100644 --- a/Core/Src/stm32c0xx_hal_msp.c +++ b/Core/Src/stm32c0xx_hal_msp.c @@ -77,79 +77,6 @@ void HAL_MspInit(void) /* USER CODE END MspInit 1 */ } -/** -* @brief ADC MSP Initialization -* This function configures the hardware resources used in this example -* @param hadc: ADC handle pointer -* @retval None -*/ -void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) -{ - GPIO_InitTypeDef GPIO_InitStruct = {0}; - RCC_PeriphCLKInitTypeDef PeriphClkInit = {0}; - if(hadc->Instance==ADC1) - { - /* USER CODE BEGIN ADC1_MspInit 0 */ - - /* USER CODE END ADC1_MspInit 0 */ - - /** Initializes the peripherals clocks - */ - PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; - PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_SYSCLK; - if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit) != HAL_OK) - { - Error_Handler(); - } - - /* Peripheral clock enable */ - __HAL_RCC_ADC_CLK_ENABLE(); - - __HAL_RCC_GPIOA_CLK_ENABLE(); - /**ADC1 GPIO Configuration - PA8 ------> ADC1_IN8 - */ - GPIO_InitStruct.Pin = GPIO_PIN_8; - GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; - GPIO_InitStruct.Pull = GPIO_NOPULL; - HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); - - /* USER CODE BEGIN ADC1_MspInit 1 */ - - /* USER CODE END ADC1_MspInit 1 */ - - } - -} - -/** -* @brief ADC MSP De-Initialization -* This function freeze the hardware resources used in this example -* @param hadc: ADC handle pointer -* @retval None -*/ -void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) -{ - if(hadc->Instance==ADC1) - { - /* USER CODE BEGIN ADC1_MspDeInit 0 */ - - /* USER CODE END ADC1_MspDeInit 0 */ - /* Peripheral clock disable */ - __HAL_RCC_ADC_CLK_DISABLE(); - - /**ADC1 GPIO Configuration - PA8 ------> ADC1_IN8 - */ - HAL_GPIO_DeInit(GPIOA, GPIO_PIN_8); - - /* USER CODE BEGIN ADC1_MspDeInit 1 */ - - /* USER CODE END ADC1_MspDeInit 1 */ - } - -} - /* USER CODE BEGIN 1 */ /* USER CODE END 1 */ diff --git a/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h b/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h deleted file mode 100644 index 07388f8..0000000 --- a/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc.h +++ /dev/null @@ -1,1934 +0,0 @@ -/** - ****************************************************************************** - * @file stm32c0xx_hal_adc.h - * @author MCD Application Team - * @brief Header file of ADC HAL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32C0xx_HAL_ADC_H -#define STM32C0xx_HAL_ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32c0xx_hal_def.h" - -/* Include low level driver */ -#include "stm32c0xx_ll_adc.h" - -/** @addtogroup STM32C0xx_HAL_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ADC_Exported_Types ADC Exported Types - * @{ - */ - -/** - * @brief ADC group regular oversampling structure definition - */ -typedef struct -{ - uint32_t Ratio; /*!< Configures the oversampling ratio. - This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ - - uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. - This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ - - uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. - This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ - -} ADC_OversamplingTypeDef; - -/** - * @brief Structure definition of ADC instance and ADC group regular. - * @note Parameters of this structure are shared within 2 scopes: - * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC - * groups regular and injected): ClockPrescaler, Resolution, DataAlign, - * ScanConvMode, EOCSelection, LowPowerAutoWait. - * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, - * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. - * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. - * ADC state can be either: - * - For all parameters: ADC disabled - * - For all parameters except 'ClockPrescaler' and 'Resolution': ADC enabled without conversion on going on - * group regular. - * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behavior in case of intended action to update another - * parameter (which fulfills the ADC state condition) on the fly). - */ -typedef struct -{ - uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous - clock derived from system clock or PLL (Refer to reference manual for list of - clocks available)) and clock prescaler. - This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. - Note: The ADC clock configuration is common to all ADC instances. - Note: In case of synchronous clock mode based on HCLK/1, the configuration must - be enabled only if the system clock has a 50% duty clock cycle (APB - prescaler configured inside RCC must be bypassed and PCLK clock must have - 50% duty cycle). Refer to reference manual for details. - Note: In case of usage of asynchronous clock, the selected clock must be - preliminarily enabled at RCC top level. - Note: This parameter can be modified only if all ADC instances are disabled. */ - - uint32_t Resolution; /*!< Configure the ADC resolution. - This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ - - uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). - Refer to reference manual for alignments formats versus resolutions. - This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ - - uint32_t ScanConvMode; /*!< Configure the sequencer of ADC group regular. - On this STM32 series, ADC group regular sequencer both modes "fully configurable" - or "not fully configurable" are available: - - sequencer configured to fully configurable: - sequencer length and each rank affectation to a channel are configurable. - - Sequence length: Set number of ranks in the scan sequence. - - Sequence direction: Unless specified in parameters, sequencer - scan direction is forward (from rank 1 to rank n). - - sequencer configured to not fully configurable: - sequencer length and each rank affectation to a channel are fixed by channel - HW number. - - Sequence length: Number of ranks in the scan sequence is - defined by number of channels set in the sequence, - rank of each channel is fixed by channel HW number. - (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - - Sequence direction: Unless specified in parameters, sequencer - scan direction is forward (from lowest channel number to - highest channel number). - This parameter can be associated to parameter 'DiscontinuousConvMode' to have - main sequence subdivided in successive parts. Sequencer is automatically enabled - if several channels are set (sequencer cannot be disabled, as it can be the case - on other STM32 devices): - If only 1 channel is set: Conversion is performed in single mode. - If several channels are set: Conversions are performed in sequence mode. - This parameter can be a value of @ref ADC_Scan_mode */ - - uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and - interruption: end of unitary conversion or end of sequence conversions. - This parameter can be a value of @ref ADC_EOCSelection. */ - - FunctionalState LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the - previous conversion (for ADC group regular) has been retrieved by user software, - using function HAL_ADC_GetValue(). - This feature automatically adapts the frequency of ADC conversions triggers to - the speed of the system that reads the data. Moreover, this avoids risk of - overrun for low frequency applications. - This parameter can be set to ENABLE or DISABLE. - Note: It is not recommended to use with interruption or DMA (HAL_ADC_Start_IT(), - HAL_ADC_Start_DMA()) since these modes have to clear immediately the EOC - flag (by CPU to free the IRQ pending event or by DMA). - Auto wait will work but fort a very short time, discarding its intended - benefit (except specific case of high load of CPU or DMA transfers which - can justify usage of auto wait). - Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, - when ADC conversion data is needed: - use HAL_ADC_PollForConversion() to ensure that conversion is completed and - HAL_ADC_GetValue() to retrieve conversion result and trig another - conversion start. */ - - FunctionalState LowPowerAutoPowerOff; /*!< Select the auto-off mode: the ADC automatically powers-off after a - conversion and automatically wakes-up when a new conversion is triggered - (with startup time between trigger and start of sampling). - This feature can be combined with automatic wait mode - (parameter 'LowPowerAutoWait'). - This parameter can be set to ENABLE or DISABLE. */ - - FunctionalState ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) - or continuous mode for ADC group regular, after the first ADC conversion - start trigger occurred (software start or external trigger). This parameter - can be set to ENABLE or DISABLE. */ - - uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group - sequencer. - This parameter is dependent on ScanConvMode: - - sequencer configured to fully configurable: - Number of ranks in the scan sequence is configurable using this parameter. - Note: After the first call of 'HAL_ADC_Init()', each rank corresponding to - parameter "NbrOfConversion" must be set using 'HAL_ADC_ConfigChannel()'. - Afterwards, when all needed sequencer ranks are set, parameter - 'NbrOfConversion' can be updated without modifying configuration of - sequencer ranks (sequencer ranks above 'NbrOfConversion' are discarded). - - sequencer configured to not fully configurable: - Number of ranks in the scan sequence is defined by number of channels set in - the sequence. This parameter is discarded. - This parameter must be a number between Min_Data = 1 and Max_Data = 8. - Note: This parameter must be modified when no conversion is on going on regular - group (ADC disabled, or ADC enabled without continuous mode or external - trigger that could launch a conversion). */ - - FunctionalState DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed - in Complete-sequence/Discontinuous-sequence (main sequence subdivided in - successive parts). - Discontinuous mode is used only if sequencer is enabled (parameter - 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. - Discontinuous mode can be enabled only if continuous mode is disabled. - If continuous mode is enabled, this parameter setting is discarded. - This parameter can be set to ENABLE or DISABLE. - Note: On this STM32 series, ADC group regular number of discontinuous - ranks increment is fixed to one-by-one. */ - - uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion - start. - If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger - is used instead. - This parameter can be a value of @ref ADC_regular_external_trigger_source. - Caution: external trigger source is common to all ADC instances. */ - - uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start - If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. - This parameter can be a value of @ref ADC_regular_external_trigger_edge */ - - FunctionalState DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA - transfer stops when number of conversions is reached) or in continuous - mode (DMA transfer unlimited, whatever number of conversions). - This parameter can be set to ENABLE or DISABLE. - Note: In continuous mode, DMA must be configured in circular mode. - Otherwise an overrun will be triggered when DMA buffer maximum - pointer is reached. */ - - uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). - This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. - Note: In case of overrun set to data preserved and usage with programming model - with interruption (HAL_Start_IT()): ADC IRQ handler has to clear end of - conversion flags, this induces the release of the preserved data. If - needed, this data can be saved in function HAL_ADC_ConvCpltCallback(), - placed in user program code (called before end of conversion flags clear) - Note: Error reporting with respect to the conversion mode: - - Usage with ADC conversion by polling for event or interruption: Error is - reported only if overrun is set to data preserved. If overrun is set to - data overwritten, user can willingly not read all the converted data, - this is not considered as an erroneous case. - - Usage with ADC conversion by DMA: Error is reported whatever overrun - setting (DMA is expected to process all data from data register). */ - - uint32_t SamplingTimeCommon1; /*!< Set sampling time common to a group of channels. - Unit: ADC clock cycles - Conversion time is the addition of sampling time and processing time - (12.5 ADC clock cycles at ADC resolution 12 bits, - 10.5 cycles at 10 bits, - 8.5 cycles at 8 bits, - 6.5 cycles at 6 bits). - Note: On this STM32 family, two different sampling time settings are available, - each channel can use one of these two settings. On some other STM32 devices - this parameter in channel wise and is located into ADC channel - initialization structure. - This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME - Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor) - sampling time constraints must be respected (sampling time can be adjusted - in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values, parameters TS_vrefint, - TS_vbat, TS_temp (values rough order: few tens of microseconds). */ - - uint32_t SamplingTimeCommon2; /*!< Set sampling time common to a group of channels, second common setting possible. - Unit: ADC clock cycles - Conversion time is the addition of sampling time and processing time - (12.5 ADC clock cycles at ADC resolution 12 bits, - 10.5 cycles at 10 bits, - 8.5 cycles at 8 bits, - 6.5 cycles at 6 bits). - Note: On this STM32 family, two different sampling time settings are available, - each channel can use one of these two settings. On some other STM32 devices - this parameter in channel wise and is located into ADC channel - initialization structure. - This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME - Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor) - sampling time constraints must be respected (sampling time can be adjusted - in function of ADC clock frequency and sampling time setting) - Refer to device datasheet for timings values, parameters TS_vrefint, - TS_vbat, TS_temp (values rough order: few tens of microseconds). */ - - FunctionalState OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. - This parameter can be set to ENABLE or DISABLE. - Note: This parameter can be modified only if there is no conversion is - ongoing on ADC group regular. */ - - ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. - Caution: this setting overwrites the previous oversampling configuration - if oversampling is already enabled. */ - - uint32_t TriggerFrequencyMode; /*!< Set ADC trigger frequency mode. - This parameter can be a value of @ref ADC_HAL_EC_REG_TRIGGER_FREQ. - Note: ADC trigger frequency mode must be set to low frequency when - a duration is exceeded before ADC conversion start trigger event - (between ADC enable and ADC conversion start trigger event - or between two ADC conversion start trigger event). - Duration value: Refer to device datasheet, parameter "tIdle". - Note: When ADC trigger frequency mode is set to low frequency, - some rearm cycles are inserted before performing ADC conversion - start, inducing a delay of 2 ADC clock cycles. */ - -} ADC_InitTypeDef; - -/** - * @brief Structure definition of ADC channel for regular group - * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. - * ADC state can be either: - * - For all parameters: ADC disabled or enabled without conversion on going on regular group. - * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed - * without error reporting (as it can be the expected behavior in case of intended action to update another - * parameter (which fulfills the ADC state condition) on the fly). - */ -typedef struct -{ - uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. - This parameter can be a value of @ref ADC_HAL_EC_CHANNEL - Note: Depending on devices and ADC instances, some channels may not be available - on device package pins. Refer to device datasheet for channels - availability. */ - - uint32_t Rank; /*!< Add or remove the channel from ADC regular group sequencer and specify its - conversion rank. - This parameter is dependent on ScanConvMode: - - sequencer configured to fully configurable: - Channels ordering into each rank of scan sequence: - whatever channel can be placed into whatever rank. - - sequencer configured to not fully configurable: - rank of each channel is fixed by channel HW number. - (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - Despite the channel rank is fixed, this parameter allow an additional - possibility: to remove the selected rank (selected channel) from sequencer. - This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS */ - - uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. - Unit: ADC clock cycles - Conversion time is the addition of sampling time and processing time - (12.5 ADC clock cycles at ADC resolution 12 bits, - 10.5 cycles at 10 bits, - 8.5 cycles at 8 bits, - 6.5 cycles at 6 bits). - This parameter can be a value of @ref ADC_HAL_EC_SAMPLINGTIME_COMMON - Note: On this STM32 family, two different sampling time settings are available - (refer to parameters "SamplingTimeCommon1" and "SamplingTimeCommon2"), - each channel can use one of these two settings. - - Note: In case of usage of internal measurement channels (VrefInt/Vbat/ - TempSensor), sampling time constraints must be respected (sampling time - can be adjusted in function of ADC clock frequency and sampling time - setting) - Refer to device datasheet for timings values. */ - -} ADC_ChannelConfTypeDef; - -/** - * @brief Structure definition of ADC analog watchdog - * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. - * ADC state can be either: - * - For all parameters except 'HighThreshold', 'LowThreshold': ADC disabled or ADC enabled without conversion - on going on ADC groups regular. - * - For parameters 'HighThreshold', 'LowThreshold': ADC enabled with conversion on going on regular. - */ -typedef struct -{ - uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. - For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels - by setting parameter 'WatchdogMode') - For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls - of 'HAL_ADC_AnalogWDGConfig()' for each channel) - This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ - - uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. - For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all - channels, ADC group regular. - For Analog Watchdog 2 and 3: Several channels can be monitored by applying - successively the AWD init structure. - This parameter can be a value of @ref ADC_analog_watchdog_mode. */ - - uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. - For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' - is configured on single channel (only 1 channel can be - monitored). - For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, - call successively the function HAL_ADC_AnalogWDGConfig() - for each channel to be added (or removed with value - 'ADC_ANALOGWATCHDOG_NONE'). - This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ - - FunctionalState ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. - This parameter can be set to ENABLE or DISABLE */ - - uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a - number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F - respectively. - Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC - resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 - LSB are ignored. - Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are - impacted: the comparison of analog watchdog thresholds is done on - oversampling final computation (after ratio and shift application): - ADC data register bitfield [15:4] (12 most significant bits). */ - - uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. - Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a - number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F - respectively. - Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC - resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 - LSB are ignored. - Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are - impacted: the comparison of analog watchdog thresholds is done on - oversampling final computation (after ratio and shift application): - ADC data register bitfield [15:4] (12 most significant bits).*/ -} ADC_AnalogWDGConfTypeDef; - -/** @defgroup ADC_States ADC States - * @{ - */ - -/** - * @brief HAL ADC state machine: ADC states definition (bitfields) - * @note ADC state machine is managed by bitfields, state must be compared - * with bit by bit. - * For example: - * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " - * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " - */ -/* States of ADC global scope */ -#define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ -#define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy from internal process (ex : calibration, ...) */ -#define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ - -/* States of ADC errors */ -#define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010UL) /*!< Internal error occurrence */ -#define HAL_ADC_STATE_ERROR_CONFIG (0x00000020UL) /*!< Configuration error occurrence */ -#define HAL_ADC_STATE_ERROR_DMA (0x00000040UL) /*!< DMA error occurrence */ - -/* States of ADC group regular */ -#define HAL_ADC_STATE_REG_BUSY (0x00000100UL) /*!< A conversion on ADC group regular is ongoing or can occur - (either by continuous mode, external trigger, low power - auto power-on (if feature available), multimode ADC master - control (if feature available)) */ -#define HAL_ADC_STATE_REG_EOC (0x00000200UL) /*!< Conversion data available on group regular */ -#define HAL_ADC_STATE_REG_OVR (0x00000400UL) /*!< Overrun occurrence */ -#define HAL_ADC_STATE_REG_EOSMP (0x00000800UL) /*!< Not available on this STM32 series: End Of Sampling flag - raised */ - -/* States of ADC group injected */ -#define HAL_ADC_STATE_INJ_BUSY (0x00001000UL) /*!< Not available on this STM32 series: A conversion on group - injected is ongoing or can occur (either by auto-injection - mode, external trigger, low power auto power-on (if feature - available), multimode ADC master control (if feature - available))*/ -#define HAL_ADC_STATE_INJ_EOC (0x00002000UL) /*!< Not available on this STM32 series: Conversion data - available on group injected */ -#define HAL_ADC_STATE_INJ_JQOVF (0x00004000UL) /*!< Not available on this STM32 series: Injected queue overflow - occurrence */ - -/* States of ADC analog watchdogs */ -#define HAL_ADC_STATE_AWD1 (0x00010000UL) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ -#define HAL_ADC_STATE_AWD2 (0x00020000UL) /*!< Not available on this STM32 series: Out-of-window occurrence - of ADC analog watchdog 2 */ -#define HAL_ADC_STATE_AWD3 (0x00040000UL) /*!< Not available on this STM32 series: Out-of-window occurrence - of ADC analog watchdog 3 */ - -/* States of ADC multi-mode */ -#define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000UL) /*!< Not available on this STM32 series: ADC in multimode slave - state, controlled by another ADC master (when feature - available) */ - - -/** - * @} - */ - -/** - * @brief ADC handle Structure definition - */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -typedef struct __ADC_HandleTypeDef -#else -typedef struct -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -{ - ADC_TypeDef *Instance; /*!< Register base address */ - ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ - DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ - HAL_LockTypeDef Lock; /*!< ADC locking object */ - __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ - __IO uint32_t ErrorCode; /*!< ADC Error code */ - - uint32_t ADCGroupRegularSequencerRanks; /*!< ADC group regular sequencer memorization of ranks - setting, used in mode "fully configurable" (refer to - parameter 'ScanConvMode') */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ - void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer - callback */ - void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ - void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ - void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ - void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ - void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ - void (* CalibrationCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of calibration callback */ - void (* ADCReadyCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Ready callback */ - void (* ChannelConfigReadyCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Channel Configuration Ready - callback */ - void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ - void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -} ADC_HandleTypeDef; - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -/** - * @brief HAL ADC Callback ID enumeration definition - */ -typedef enum -{ - HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ - HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ - HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ - HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ - HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ - HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ - HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ - HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ - HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ -} HAL_ADC_CallbackIDTypeDef; - -/** - * @brief HAL ADC Callback pointer definition - */ -typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ - -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - -/** - * @} - */ - - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Constants ADC Exported Constants - * @{ - */ - -/** @defgroup ADC_Error_Code ADC Error Code - * @{ - */ -#define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ -#define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC peripheral internal error (problem of clocking, - enable/disable, erroneous state, ...) */ -#define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ -#define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -#define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source - * @{ - */ -#define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock - without prescaler. This configuration must be enabled only if PCLK has - a 50% duty clock cycle (APB prescaler configured inside the RCC must - be bypassed and the system clock must by 50% duty cycle) */ -#define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock - with prescaler division by 2 */ -#define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock - with prescaler division by 4 */ - -#define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without - prescaler */ -#define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler - division by 2 */ -#define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler - division by 4 */ -#define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler - division by 6 */ -#define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler - division by 8 */ -#define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler - division by 10 */ -#define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler - division by 12 */ -#define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler - division by 16 */ -#define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler - division by 32 */ -#define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler - division by 64 */ -#define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler - division by 128 */ -#define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler - division by 256 */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution - * @{ - */ -#define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ -#define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ -#define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ -#define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment - * @{ - */ -#define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned - (alignment on data register LSB bit 0)*/ -#define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned - (alignment on data register MSB bit 15)*/ -/** - * @} - */ - -/** @defgroup ADC_Scan_mode ADC sequencer scan mode - * @{ - */ -/* Note: On this STM32 family, ADC group regular sequencer both modes */ -/* "fully configurable" or "not fully configurable" are */ -/* available. */ -/* Scan mode values must be compatible with other STM32 devices having */ -/* a configurable sequencer. */ -/* Scan direction setting values are defined by taking in account */ -/* already defined values for other STM32 devices: */ -/* ADC_SCAN_DISABLE (0x00000000UL) */ -/* ADC_SCAN_ENABLE (0x00000001UL) */ -/* Sequencer fully configurable with only rank 1 enabled is considered */ -/* as default setting equivalent to scan enable. */ -/* In case of migration from another STM32 device, the user will be */ -/* warned of change of setting choices with assert check. */ -/* Sequencer set to fully configurable */ -#define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: - only the rank 1 is enabled (no scan sequence on several ranks) */ -#define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: - sequencer length and each rank affectation to a channel are configurable. */ - -/* Sequencer set to not fully configurable */ -#define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: - sequencer length and each rank affectation to a channel are fixed by - channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - Scan direction forward: from channel 0 to channel 18 */ -#define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT \ - | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: - sequencer length and each rank affectation to a channel are fixed by - channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - Scan direction backward: from channel 18 to channel 0 */ - -#define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 series */ -#define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 series */ -/** - * @} - */ - -/** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source - * @{ - */ -/* ADC group regular trigger sources for all ADC instances */ -#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion - trigger internal: SW start. */ -#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion - trigger from external peripheral: TIM1 TRGO. - Trigger edge set to rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion - trigger from external peripheral: TIM1 channel 4 event - (capture compare: input capture or output capture). - Trigger edge set to rising edge (default setting). */ -#if defined(TIM2) -#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion - trigger from external peripheral: TIM2 TRGO. - Trigger edge set to rising edge (default setting). */ -#endif /* TIM2 */ -#define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion - trigger from external peripheral: TIM3 TRGO. - Trigger edge set to rising edge (default setting). */ -#if defined(TIM4) -#define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_TRGO) /*!< ADC group regular conversion - trigger from external peripheral: TIM4 TRGO. - Trigger edge set to rising edge (default setting). */ -#endif /* TIM4 */ -#if defined(TIM6) -#define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion - trigger from external peripheral: TIM6 TRGO. - Trigger edge set to rising edge (default setting). */ -#endif /* TIM6 */ -#if defined(TIM15) -#define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion - trigger from external peripheral: TIM15 TRGO. - Trigger edge set to rising edge (default setting). */ -#endif /* TIM15 */ -#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion - trigger from external peripheral: external interrupt line 11. - Trigger edge set to rising edge (default setting). */ -/** - * @} - */ - -/** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) - * @{ - */ -#define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< Regular conversions hardware - trigger detection disabled */ -#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion - trigger polarity set to rising edge */ -#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion - trigger polarity set to falling edge */ -#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion - trigger polarity set to both rising and falling edges */ -/** - * @} - */ - -/** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions - * @{ - */ -#define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ -#define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data - * @{ - */ -#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case - of overrun: data preserved */ -#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case - of overrun: data overwritten */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks - * @{ - */ -#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Setting relevant if parameter "ScanConvMode" is set - to sequencer not fully configurable: Enable the rank of the selected - channels. Number of ranks in the sequence is defined by number of channels - enabled, rank of each channel is defined by channel number - (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...) */ -#define ADC_RANK_NONE (0x00000002U) /*!< Setting relevant if parameter "ScanConvMode" - is set to sequencer not fully configurable: Disable the selected rank - (selected channel) from sequencer */ - -#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ -#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ -#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ -#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ -#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ -#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ -#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ -#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels - * @{ - */ -#define ADC_SAMPLINGTIME_COMMON_1 (LL_ADC_SAMPLINGTIME_COMMON_1) /*!< Set sampling time common to a group of - channels: sampling time nb 1 */ -#define ADC_SAMPLINGTIME_COMMON_2 (LL_ADC_SAMPLINGTIME_COMMON_2) /*!< Set sampling time common to a group of - channels: sampling time nb 2 */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time - * @{ - */ -#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ -#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ -#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ -#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ -#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ -#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ -#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */ -#define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number - * @{ - */ -#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ -#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ -#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ -#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ -#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ -#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ -#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ -#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ -#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ -#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ -#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ -#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ -#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ -#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ -#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */ -#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */ -#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */ -#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */ -#define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< External channel (GPIO pin) ADCx_IN18 */ -#define ADC_CHANNEL_19 (LL_ADC_CHANNEL_19) /*!< External channel (GPIO pin) ADCx_IN19 */ -#define ADC_CHANNEL_20 (LL_ADC_CHANNEL_20) /*!< External channel (GPIO pin) ADCx_IN20 */ -#define ADC_CHANNEL_21 (LL_ADC_CHANNEL_21) /*!< External channel (GPIO pin) ADCx_IN21 */ -#define ADC_CHANNEL_22 (LL_ADC_CHANNEL_22) /*!< External channel (GPIO pin) ADCx_IN22 */ -#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: - Internal voltage reference. */ -#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor. */ -#define ADC_CHANNEL_VDDA (LL_ADC_CHANNEL_VDDA) /*!< Internal channel VDDA */ -#define ADC_CHANNEL_VSSA (LL_ADC_CHANNEL_VSSA) /*!< Internal channel VSSA */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number - * @{ - */ -#define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ -#define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ -#define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ -/** - * @} - */ - -/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode - * @{ - */ -#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */ -#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to a regular - group single channel */ -#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to regular - group all channels */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio - * @{ - */ -/** - * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed - * to result as the ADC oversampling conversion data (before potential shift) - */ -#define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */ -#define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */ -#define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio 8 */ -#define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio 16 */ -#define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio 32 */ -#define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio 64 */ -#define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio 128 */ -#define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio 256 */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift - * @{ - */ -/** - * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling - * conversion data) - */ -#define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ -#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */ -#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */ -#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */ -#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */ -#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */ -#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */ -#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */ -#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode - * @{ - */ -#define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: - continuous mode (all conversions of OVS ratio are done from 1 trigger) */ -#define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: - discontinuous mode (each conversion of OVS ratio needs a trigger) */ -/** - * @} - */ - -/** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode - * @{ - */ - -/** - * @note ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion - * start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion - * start trigger event). - * Duration value: Refer to device datasheet, parameter "tIdle". - */ -#define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< Trigger frequency mode set to high frequency. */ -#define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< Trigger frequency mode set to low frequency. */ -/** - * @} - */ - -/** @defgroup ADC_Event_type ADC Event type - * @{ - */ -/** - * @note Analog watchdog 1 is available on all stm32 series - * Analog watchdog 2 and 3 are not available on all series - */ -#define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ -#define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ -#define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog) */ -#define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog) */ -#define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ -/** - * @} - */ -#define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility - with other STM32 devices having only one analog watchdog */ - -/** @defgroup ADC_interrupts_definition ADC interrupts definition - * @{ - */ -#define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ -#define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */ -#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ -#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ -#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ -#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ -#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ -#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog - watchdog) */ -#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog - watchdog) */ -#define ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC End of Calibration interrupt source */ -/** - * @} - */ - -/** @defgroup ADC_flags_definition ADC flags definition - * @{ - */ -#define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ -#define ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC channel configuration ready flag */ -#define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ -#define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ -#define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ -#define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ -#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag */ -#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag */ -#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag */ -#define ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC End of Calibration interrupt flag */ -/** - * @} - */ - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ - -/** @defgroup ADC_Private_Macros ADC Private Macros - * @{ - */ -/* Macro reserved for internal HAL driver usage, not intended to be used in */ -/* code of final user. */ - -/** - * @brief Test if conversion trigger of regular group is software start - * or external trigger. - * @param __HANDLE__ ADC handle - * @retval SET (software start) or RESET (external trigger) - */ -#define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ - (((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_EXTEN) == 0UL) - -/** - * @brief Return resolution bits in CFGR1 register RES[1:0] field. - * @param __HANDLE__ ADC handle - * @retval Value of bitfield RES in CFGR1 register. - */ -#define ADC_GET_RESOLUTION(__HANDLE__) \ - (LL_ADC_GetResolution((__HANDLE__)->Instance)) - -/** - * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). - * @param __HANDLE__ ADC handle - * @retval None - */ -#define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) - -/** - * @brief Simultaneously clear and set specific bits of the handle State. - * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), - * the first parameter is the ADC handle State, the second parameter is the - * bit field to clear, the third and last parameter is the bit field to set. - * @retval None - */ -#define ADC_STATE_CLR_SET MODIFY_REG - -/** - * @brief Enable ADC discontinuous conversion mode for regular group - * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode. - * @retval None - */ -#define ADC_CFGR1_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) \ - ((_REG_DISCONTINUOUS_MODE_) << 16U) - -/** - * @brief Enable the ADC auto off mode. - * @param _AUTOOFF_ Auto off bit enable or disable. - * @retval None - */ -#define ADC_CFGR1_AUTOOFF(_AUTOOFF_) \ - ((_AUTOOFF_) << 15U) - -/** - * @brief Enable the ADC auto delay mode. - * @param _AUTOWAIT_ Auto delay bit enable or disable. - * @retval None - */ -#define ADC_CFGR1_AUTOWAIT(_AUTOWAIT_) \ - ((_AUTOWAIT_) << 14U) - -/** - * @brief Enable ADC continuous conversion mode. - * @param _CONTINUOUS_MODE_ Continuous mode. - * @retval None - */ -#define ADC_CFGR1_CONTINUOUS(_CONTINUOUS_MODE_) \ - ((_CONTINUOUS_MODE_) << 13U) - -/** - * @brief Enable ADC overrun mode. - * @param _OVERRUN_MODE_ Overrun mode. - * @retval Overrun bit setting to be programmed into CFGR register - */ -/* Note: Bit ADC_CFGR1_OVRMOD not used directly in constant */ -/* "ADC_OVR_DATA_OVERWRITTEN" to have this case defined to 0x00, to set it */ -/* as the default case to be compliant with other STM32 devices. */ -#define ADC_CFGR1_OVERRUN(_OVERRUN_MODE_) \ - ( ( (_OVERRUN_MODE_) != (ADC_OVR_DATA_PRESERVED) \ - )? (ADC_CFGR1_OVRMOD) : (0x00000000UL) \ - ) - -/** - * @brief Set ADC scan mode with differentiation of sequencer setting - * fixed or configurable - * @param _SCAN_MODE_ Scan conversion mode. - * @retval None - */ -/* Note: Scan mode set using this macro (instead of parameter direct set) */ -/* due to different modes on other STM32 devices: */ -/* if scan mode is disabled, sequencer is set to fully configurable */ -/* with setting of only rank 1 enabled afterwards. */ -#define ADC_SCAN_SEQ_MODE(_SCAN_MODE_) \ - ( (((_SCAN_MODE_) & ADC_SCAN_SEQ_FIXED_INT) != 0UL \ - )? \ - ((_SCAN_MODE_) & (~ADC_SCAN_SEQ_FIXED_INT)) \ - : \ - (ADC_CFGR1_CHSELRMOD) \ - ) - -/** - * @brief Enable the ADC DMA continuous request. - * @param _DMACONTREQ_MODE_: DMA continuous request mode. - * @retval None - */ -#define ADC_CFGR1_DMACONTREQ(_DMACONTREQ_MODE_) \ - ((_DMACONTREQ_MODE_) << 1U) - -/** - * @brief Shift the AWD threshold in function of the selected ADC resolution. - * Thresholds have to be left-aligned on bit 11, the LSB (right bits) are set to 0. - * If resolution 12 bits, no shift. - * If resolution 10 bits, shift of 2 ranks on the left. - * If resolution 8 bits, shift of 4 ranks on the left. - * If resolution 6 bits, shift of 6 ranks on the left. - * therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2)) - * @param __HANDLE__ ADC handle - * @param _Threshold_ Value to be shifted - * @retval None - */ -#define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_) \ - ((_Threshold_) << ((((__HANDLE__)->Instance->CFGR1 & ADC_CFGR1_RES) >> 3U)*2U)) - -#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV1) ||\ - ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV2) ||\ - ((ADC_CLOCK) == ADC_CLOCK_SYNC_PCLK_DIV4) ||\ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1 ) ||\ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2 ) ||\ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4 ) ||\ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV6 ) ||\ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV8 ) ||\ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV10 ) ||\ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV12 ) ||\ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV16 ) ||\ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV32 ) ||\ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV64 ) ||\ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV128 ) ||\ - ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV256)) - -#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION_12B) || \ - ((RESOLUTION) == ADC_RESOLUTION_10B) || \ - ((RESOLUTION) == ADC_RESOLUTION_8B) || \ - ((RESOLUTION) == ADC_RESOLUTION_6B) ) - -#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \ - ((ALIGN) == ADC_DATAALIGN_LEFT) ) - -#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \ - ((SCAN_MODE) == ADC_SCAN_ENABLE) || \ - ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED) || \ - ((SCAN_MODE) == ADC_SCAN_SEQ_FIXED_BACKWARD) ) - -#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ - ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) - -#if defined(TIM2) -#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \ - ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIG_T2_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \ - ((REGTRIG) == ADC_SOFTWARE_START)) -#else -#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIG_T1_TRGO2) || \ - ((REGTRIG) == ADC_EXTERNALTRIG_T1_CC4) || \ - ((REGTRIG) == ADC_EXTERNALTRIG_T3_TRGO) || \ - ((REGTRIG) == ADC_EXTERNALTRIG_EXT_IT11) || \ - ((REGTRIG) == ADC_SOFTWARE_START)) -#endif /* TIM2 */ - -#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV) || \ - ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)) - -#define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED) || \ - ((OVR) == ADC_OVR_DATA_OVERWRITTEN) ) - -#define IS_ADC_REGULAR_RANK_SEQ_FIXED(RANK) (((RANK) == ADC_RANK_CHANNEL_NUMBER) || \ - ((RANK) == ADC_RANK_NONE) ) - -#define IS_ADC_REGULAR_RANK(RANK) (((RANK) == ADC_REGULAR_RANK_1 ) || \ - ((RANK) == ADC_REGULAR_RANK_2 ) || \ - ((RANK) == ADC_REGULAR_RANK_3 ) || \ - ((RANK) == ADC_REGULAR_RANK_4 ) || \ - ((RANK) == ADC_REGULAR_RANK_5 ) || \ - ((RANK) == ADC_REGULAR_RANK_6 ) || \ - ((RANK) == ADC_REGULAR_RANK_7 ) || \ - ((RANK) == ADC_REGULAR_RANK_8 ) ) - -#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0) || \ - ((CHANNEL) == ADC_CHANNEL_1) || \ - ((CHANNEL) == ADC_CHANNEL_2) || \ - ((CHANNEL) == ADC_CHANNEL_3) || \ - ((CHANNEL) == ADC_CHANNEL_4) || \ - ((CHANNEL) == ADC_CHANNEL_5) || \ - ((CHANNEL) == ADC_CHANNEL_6) || \ - ((CHANNEL) == ADC_CHANNEL_7) || \ - ((CHANNEL) == ADC_CHANNEL_8) || \ - ((CHANNEL) == ADC_CHANNEL_9) || \ - ((CHANNEL) == ADC_CHANNEL_10) || \ - ((CHANNEL) == ADC_CHANNEL_11) || \ - ((CHANNEL) == ADC_CHANNEL_12) || \ - ((CHANNEL) == ADC_CHANNEL_13) || \ - ((CHANNEL) == ADC_CHANNEL_14) || \ - ((CHANNEL) == ADC_CHANNEL_15) || \ - ((CHANNEL) == ADC_CHANNEL_16) || \ - ((CHANNEL) == ADC_CHANNEL_17) || \ - ((CHANNEL) == ADC_CHANNEL_18) || \ - ((CHANNEL) == ADC_CHANNEL_19) || \ - ((CHANNEL) == ADC_CHANNEL_20) || \ - ((CHANNEL) == ADC_CHANNEL_21) || \ - ((CHANNEL) == ADC_CHANNEL_22) || \ - ((CHANNEL) == ADC_CHANNEL_TEMPSENSOR) || \ - ((CHANNEL) == ADC_CHANNEL_VREFINT) || \ - ((CHANNEL) == ADC_CHANNEL_VDDA) || \ - ((CHANNEL) == ADC_CHANNEL_VSSA) ) - -#define IS_ADC_SAMPLING_TIME_COMMON(SAMPLING_TIME_COMMON) (((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_1) || \ - ((SAMPLING_TIME_COMMON) == ADC_SAMPLINGTIME_COMMON_2) ) - -#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_1CYCLE_5) || \ - ((TIME) == ADC_SAMPLETIME_3CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_7CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_12CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_19CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_39CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_79CYCLES_5) || \ - ((TIME) == ADC_SAMPLETIME_160CYCLES_5) ) - -#define IS_ADC_ANALOG_WATCHDOG_NUMBER(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_1) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_2) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_3) ) - -#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \ - ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG) ) - -#define IS_ADC_TRIGGER_FREQ(TRIGGER_FREQ) (((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_HIGH) || \ - ((TRIGGER_FREQ) == LL_ADC_TRIGGER_FREQ_LOW) ) - -#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == ADC_EOSMP_EVENT) || \ - ((EVENT) == ADC_AWD1_EVENT) || \ - ((EVENT) == ADC_AWD2_EVENT) || \ - ((EVENT) == ADC_AWD3_EVENT) || \ - ((EVENT) == ADC_OVR_EVENT) ) - -/** - * @brief Verify that a given value is aligned with the ADC resolution range. - * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). - * @param __ADC_VALUE__ value checked against the resolution. - * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) - */ -#define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ - ((__ADC_VALUE__) <= __LL_ADC_DIGITAL_SCALE(__RESOLUTION__)) - -/** @defgroup ADC_regular_nb_conv_verification ADC Regular Conversion Number Verification - * @{ - */ -#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= 1UL) && ((LENGTH) <= 8UL)) -/** - * @} - */ - - -/* Private constants ---------------------------------------------------------*/ - -/** @defgroup ADC_Private_Constants ADC Private Constants - * @{ - */ - -/* Combination of all post-conversion flags bits: EOC/EOS, OVR, AWD */ -#define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_AWD | ADC_FLAG_OVR | ADC_FLAG_EOS | ADC_FLAG_EOC) - -/* Internal definition to differentiate sequencer setting fixed or configurable */ -#define ADC_SCAN_SEQ_FIXED_INT 0x80000000U - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Macros ADC Exported Macros - * @{ - */ -/* Macro for internal HAL driver usage, and possibly can be used into code of */ -/* final user. */ - -/** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. - * @{ - */ - -/** @brief Reset ADC handle state. - * @param __HANDLE__ ADC handle - * @retval None - */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ - do{ \ - (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) -#else -#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ - ((__HANDLE__)->State = HAL_ADC_STATE_RESET) -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - -/** - * @brief Enable ADC interrupt. - * @param __HANDLE__ ADC handle - * @param __INTERRUPT__ ADC Interrupt - * This parameter can be one of the following values: - * @arg @ref ADC_IT_RDY ADC Ready interrupt source - * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source - * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source - * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source - * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source - * @arg @ref ADC_IT_OVR ADC overrun interrupt source - * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) - * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @retval None - */ -#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) - -/** - * @brief Disable ADC interrupt. - * @param __HANDLE__ ADC handle - * @param __INTERRUPT__ ADC Interrupt - * This parameter can be one of the following values: - * @arg @ref ADC_IT_RDY ADC Ready interrupt source - * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source - * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source - * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source - * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source - * @arg @ref ADC_IT_OVR ADC overrun interrupt source - * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) - * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @retval None - */ -#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) - -/** @brief Checks if the specified ADC interrupt source is enabled or disabled. - * @param __HANDLE__ ADC handle - * @param __INTERRUPT__ ADC interrupt source to check - * This parameter can be one of the following values: - * @arg @ref ADC_IT_RDY ADC Ready interrupt source - * @arg @ref ADC_IT_CCRDY ADC channel configuration ready interrupt source - * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source - * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source - * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source - * @arg @ref ADC_IT_OVR ADC overrun interrupt source - * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) - * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) - * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) - * @retval State of interruption (SET or RESET) - */ -#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ - (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) - -/** - * @brief Check whether the specified ADC flag is set or not. - * @param __HANDLE__ ADC handle - * @param __FLAG__ ADC flag - * This parameter can be one of the following values: - * @arg @ref ADC_FLAG_RDY ADC Ready flag - * @arg @ref ADC_FLAG_CCRDY ADC channel configuration ready flag - * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag - * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag - * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag - * @arg @ref ADC_FLAG_OVR ADC overrun flag - * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) - * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) - * @retval State of flag (TRUE or FALSE). - */ -#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ - ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) - -/** - * @brief Clear the specified ADC flag. - * @param __HANDLE__ ADC handle - * @param __FLAG__ ADC flag - * This parameter can be one of the following values: - * @arg @ref ADC_FLAG_RDY ADC Ready flag - * @arg @ref ADC_FLAG_CCRDY ADC channel configuration ready flag - * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag - * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag - * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag - * @arg @ref ADC_FLAG_OVR ADC overrun flag - * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) - * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) - * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) - * @retval None - */ -/* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ -#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ - (((__HANDLE__)->Instance->ISR) = (__FLAG__)) - -/** - * @} - */ - -/** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro - * @{ - */ - -/** - * @brief Helper macro to get ADC channel number in decimal format - * from literals ADC_CHANNEL_x. - * @note Example: - * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) - * will return decimal number "4". - * @note The input can be a value from functions where a channel - * number is returned, either defined with number - * or with bitfield (only one bit must be set). - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - * @retval Value between Min_Data=0 and Max_Data=18 - */ -#define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) - -/** - * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x - * from number in decimal format. - * @note Example: - * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) - * will return a data equivalent to "ADC_CHANNEL_4". - * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 - * @retval Returned value can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - */ -#define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) - -/** - * @brief Helper macro to determine whether the selected channel - * corresponds to literal definitions of driver. - * @note The different literal definitions of ADC channels are: - * - ADC internal channel: - * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... - * - ADC external channel (channel connected to a GPIO pin): - * ADC_CHANNEL_1, ADC_CHANNEL_2, ... - * @note The channel parameter must be a value defined from literal - * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, - * ADC_CHANNEL_TEMPSENSOR, ...), - * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), - * must not be a value from functions where a channel number is - * returned from ADC registers, - * because internal and external channels share the same channel - * number in ADC registers. The differentiation is made only with - * parameters definitions of driver. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - * @retval Value "0" if the channel corresponds to a parameter definition of a - * ADC external channel (channel connected to a GPIO pin). - * Value "1" if the channel corresponds to a parameter definition of - * a ADC internal channel. - */ -#define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ - __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) - -/** - * @brief Helper macro to convert a channel defined from parameter - * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, - * ADC_CHANNEL_TEMPSENSOR, ...), - * to its equivalent parameter definition of a ADC external channel - * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). - * @note The channel parameter can be, additionally to a value - * defined from parameter definition of a ADC internal channel - * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), - * a value defined from parameter definition of - * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) - * or a value from functions where a channel number is returned - * from ADC registers. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - * @retval Returned value can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 - * @arg @ref ADC_CHANNEL_9 - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 - * @arg @ref ADC_CHANNEL_16 - * @arg @ref ADC_CHANNEL_17 - * @arg @ref ADC_CHANNEL_18 - * @arg @ref ADC_CHANNEL_19 - * @arg @ref ADC_CHANNEL_20 - * @arg @ref ADC_CHANNEL_21 - * @arg @ref ADC_CHANNEL_22 - */ -#define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ - __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) - -/** - * @brief Helper macro to determine whether the internal channel - * selected is available on the ADC instance selected. - * @note The channel parameter must be a value defined from parameter - * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, - * ADC_CHANNEL_TEMPSENSOR, ...), - * must not be a value defined from parameter definition of - * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) - * or a value from functions where a channel number is - * returned from ADC registers, - * because internal and external channels share the same channel - * number in ADC registers. The differentiation is made only with - * parameters definitions of driver. - * @param __ADC_INSTANCE__ ADC instance - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_VREFINT - * @arg @ref ADC_CHANNEL_TEMPSENSOR - * @arg @ref ADC_CHANNEL_VDDA - * @arg @ref ADC_CHANNEL_VSSA - * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. - * Value "1" if the internal channel selected is available on the ADC instance selected. - */ -#define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ - __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) - -/** - * @brief Helper macro to select the ADC common instance - * to which is belonging the selected ADC instance. - * @note ADC common register instance can be used for: - * - Set parameters common to several ADC instances - * - Multimode (for devices with several ADC instances) - * Refer to functions having argument "ADCxy_COMMON" as parameter. - * @param __ADCx__ ADC instance - * @retval ADC common register instance - */ -#define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ - __LL_ADC_COMMON_INSTANCE((__ADCx__)) - -/** - * @brief Helper macro to check if all ADC instances sharing the same - * ADC common instance are disabled. - * @note This check is required by functions with setting conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * Refer to functions having argument "ADCxy_COMMON" as parameter. - * @note On devices with only 1 ADC common instance, parameter of this macro - * is useless and can be ignored (parameter kept for compatibility - * with devices featuring several ADC common instances). - * @param __ADCXY_COMMON__ ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Value "0" if all ADC instances sharing the same ADC common instance - * are disabled. - * Value "1" if at least one ADC instance sharing the same ADC common instance - * is enabled. - */ -#define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) - -/** - * @brief Helper macro to define the ADC conversion data full-scale digital - * value corresponding to the selected ADC resolution. - * @note ADC conversion data full-scale corresponds to voltage range - * determined by analog voltage references Vref+ and Vref- - * (refer to reference manual). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref ADC_RESOLUTION_12B - * @arg @ref ADC_RESOLUTION_10B - * @arg @ref ADC_RESOLUTION_8B - * @arg @ref ADC_RESOLUTION_6B - * @retval ADC conversion data full-scale digital value - */ -#define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) - -/** - * @brief Helper macro to convert the ADC conversion data from - * a resolution to another resolution. - * @param __DATA__ ADC conversion data to be converted - * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted - * This parameter can be one of the following values: - * @arg @ref ADC_RESOLUTION_12B - * @arg @ref ADC_RESOLUTION_10B - * @arg @ref ADC_RESOLUTION_8B - * @arg @ref ADC_RESOLUTION_6B - * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion - * This parameter can be one of the following values: - * @arg @ref ADC_RESOLUTION_12B - * @arg @ref ADC_RESOLUTION_10B - * @arg @ref ADC_RESOLUTION_8B - * @arg @ref ADC_RESOLUTION_6B - * @retval ADC conversion data to the requested resolution - */ -#define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ - __ADC_RESOLUTION_CURRENT__,\ - __ADC_RESOLUTION_TARGET__) \ -__LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ - (__ADC_RESOLUTION_CURRENT__),\ - (__ADC_RESOLUTION_TARGET__)) - -/** - * @brief Helper macro to calculate the voltage (unit: mVolt) - * corresponding to a ADC conversion data (unit: digital value). - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) - * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) - * (unit: digital value). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref ADC_RESOLUTION_12B - * @arg @ref ADC_RESOLUTION_10B - * @arg @ref ADC_RESOLUTION_8B - * @arg @ref ADC_RESOLUTION_6B - * @retval ADC conversion data equivalent voltage value (unit: mVolt) - */ -#define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ - __ADC_DATA__,\ - __ADC_RESOLUTION__) \ -__LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ - (__ADC_DATA__),\ - (__ADC_RESOLUTION__)) - -/** - * @brief Helper macro to calculate analog reference voltage (Vref+) - * (unit: mVolt) from ADC conversion data of internal voltage - * reference VrefInt. - * @note Computation is using VrefInt calibration value - * stored in system memory for each device during production. - * @note This voltage depends on user board environment: voltage level - * connected to pin Vref+. - * On devices with small package, the pin Vref+ is not present - * and internally bonded to pin Vdda. - * @note On this STM32 series, calibration data of internal voltage reference - * VrefInt corresponds to a resolution of 12 bits, - * this is the recommended ADC resolution to convert voltage of - * internal voltage reference VrefInt. - * Otherwise, this macro performs the processing to scale - * ADC conversion data to 12 bits. - * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) - * of internal voltage reference VrefInt (unit: digital value). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref ADC_RESOLUTION_12B - * @arg @ref ADC_RESOLUTION_10B - * @arg @ref ADC_RESOLUTION_8B - * @arg @ref ADC_RESOLUTION_6B - * @retval Analog reference voltage (unit: mV) - */ -#define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ - __ADC_RESOLUTION__) \ -__LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ - (__ADC_RESOLUTION__)) - -/** - * @brief Helper macro to calculate the temperature (unit: degree Celsius) - * from ADC conversion data of internal temperature sensor. - * @note Computation is using temperature sensor typical values - * (refer to device datasheet). - * @note Calculation formula: - * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) - * / Avg_Slope + CALx_TEMP - * with TS_ADC_DATA = temperature sensor raw data measured by ADC - * (unit: digital value) - * Avg_Slope = temperature sensor slope - * (unit: uV/Degree Celsius) - * TS_TYP_CALx_VOLT = temperature sensor digital value at - * temperature CALx_TEMP (unit: mV) - * Caution: Calculation relevancy under reserve the temperature sensor - * of the current device has characteristics in line with - * datasheet typical values. - * @note: On this STM32 series, calibtation parameter TS_CAL1 can be used - * to improve calculation accuracy. - * Refer to @ref TEMPSENSOR_CAL1_ADDR. - * @note As calculation input, the analog reference voltage (Vref+) must be - * defined as it impacts the ADC LSB equivalent voltage. - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note ADC measurement data must correspond to a resolution of 12bits - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value - * (unit: uV/DegCelsius). - * On this STM32 series, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at - * temperature and Vref+ defined in parameters below) (unit: mV). - * On this STM32 series, refer to device datasheet parameter "V30" - * (corresponding to TS_CAL1). - * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see - * parameter above) is corresponding (unit: mV) - * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) - * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). - * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. - * This parameter can be one of the following values: - * @arg @ref ADC_RESOLUTION_12B - * @arg @ref ADC_RESOLUTION_10B - * @arg @ref ADC_RESOLUTION_8B - * @arg @ref ADC_RESOLUTION_6B - * @retval Temperature (unit: degree Celsius) - */ -#define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ - __TEMPSENSOR_TYP_CALX_V__,\ - __TEMPSENSOR_CALX_TEMP__,\ - __VREFANALOG_VOLTAGE__,\ - __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ -__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ - (__TEMPSENSOR_TYP_CALX_V__),\ - (__TEMPSENSOR_CALX_TEMP__),\ - (__VREFANALOG_VOLTAGE__),\ - (__TEMPSENSOR_ADC_DATA__),\ - (__ADC_RESOLUTION__)) - -/** - * @} - */ - -/** - * @} - */ - -/* Include ADC HAL Extended module */ -#include "stm32c0xx_hal_adc_ex.h" - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup ADC_Exported_Functions - * @{ - */ - -/** @addtogroup ADC_Exported_Functions_Group1 - * @brief Initialization and Configuration functions - * @{ - */ -/* Initialization and de-initialization functions ****************************/ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); -void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc); -void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc); - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -/* Callbacks Register/UnRegister functions ***********************************/ -HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, - pADC_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -/** - * @} - */ - -/** @addtogroup ADC_Exported_Functions_Group2 - * @brief IO operation functions - * @{ - */ -/* IO operation functions *****************************************************/ - -/* Blocking mode: Polling */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout); -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout); - -/* Non-blocking mode: Interruption */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc); - -/* Non-blocking mode: DMA */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length); -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); - -/* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); - -/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); -void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc); -void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc); -void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc); -void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); -void HAL_ADC_CalibrationCpltCallback(ADC_HandleTypeDef *hadc); -void HAL_ADC_ADCReadyCallback(ADC_HandleTypeDef *hadc); -/** - * @} - */ - -/** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *sConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *AnalogWDGConfig); - -/** - * @} - */ - -/* Peripheral State functions *************************************************/ -/** @addtogroup ADC_Exported_Functions_Group4 - * @{ - */ -uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); -uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); - -/** - * @} - */ - -/** - * @} - */ - -/* Private functions ---------------------------------------------------------*/ -HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - - -#endif /* STM32C0xx_HAL_ADC_H */ diff --git a/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h b/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h deleted file mode 100644 index 57ccdeb..0000000 --- a/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_hal_adc_ex.h +++ /dev/null @@ -1,185 +0,0 @@ -/** - ****************************************************************************** - * @file stm32c0xx_hal_adc_ex.h - * @author MCD Application Team - * @brief Header file of ADC HAL extended module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32C0xx_HAL_ADC_EX_H -#define STM32C0xx_HAL_ADC_EX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32c0xx_hal_def.h" - -/** @addtogroup STM32C0xx_HAL_Driver - * @{ - */ - -/** @addtogroup ADCEx - * @{ - */ - -/* Exported types ------------------------------------------------------------*/ -/** @defgroup ADCEx_Exported_Types ADC Extended Exported Types - * @{ - */ - -/** - * @} - */ - -/* Exported constants --------------------------------------------------------*/ - -/** @defgroup ADCEx_Exported_Constants ADC Extended Exported Constants - * @{ - */ - -/** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups - * @{ - */ -#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macros -----------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ - -/** @defgroup ADCEx_Private_Macro_internal_HAL_driver ADC Extended Private Macros - * @{ - */ -/* Macro reserved for internal HAL driver usage, not intended to be used in */ -/* code of final user. */ - -/** - * @brief Check whether or not ADC is independent. - * @param __HANDLE__ ADC handle. - * @note When multimode feature is not available, the macro always returns SET. - * @retval SET (ADC is independent) or RESET (ADC is not). - */ -#define ADC_IS_INDEPENDENT(__HANDLE__) (SET) - - -/** - * @brief Calibration factor size verification (7 bits maximum). - * @param __CALIBRATION_FACTOR__ Calibration factor value. - * @retval SET (__CALIBRATION_FACTOR__ is within the authorized size) or RESET (__CALIBRATION_FACTOR__ is too large) - */ -#define IS_ADC_CALFACT(__CALIBRATION_FACTOR__) ((__CALIBRATION_FACTOR__) <= (0x7FU)) - -/** - * @brief Verify the ADC oversampling ratio. - * @param __RATIO__ programmed ADC oversampling ratio. - * @retval SET (__RATIO__ is a valid value) or RESET (__RATIO__ is invalid) - */ -#define IS_ADC_OVERSAMPLING_RATIO(__RATIO__) (((__RATIO__) == ADC_OVERSAMPLING_RATIO_2 ) || \ - ((__RATIO__) == ADC_OVERSAMPLING_RATIO_4 ) || \ - ((__RATIO__) == ADC_OVERSAMPLING_RATIO_8 ) || \ - ((__RATIO__) == ADC_OVERSAMPLING_RATIO_16 ) || \ - ((__RATIO__) == ADC_OVERSAMPLING_RATIO_32 ) || \ - ((__RATIO__) == ADC_OVERSAMPLING_RATIO_64 ) || \ - ((__RATIO__) == ADC_OVERSAMPLING_RATIO_128 ) || \ - ((__RATIO__) == ADC_OVERSAMPLING_RATIO_256 )) - -/** - * @brief Verify the ADC oversampling shift. - * @param __SHIFT__ programmed ADC oversampling shift. - * @retval SET (__SHIFT__ is a valid value) or RESET (__SHIFT__ is invalid) - */ -#define IS_ADC_RIGHT_BIT_SHIFT(__SHIFT__) (((__SHIFT__) == ADC_RIGHTBITSHIFT_NONE) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_1 ) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_2 ) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_3 ) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_4 ) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_5 ) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_6 ) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_7 ) || \ - ((__SHIFT__) == ADC_RIGHTBITSHIFT_8 )) - -/** - * @brief Verify the ADC oversampling triggered mode. - * @param __MODE__ programmed ADC oversampling triggered mode. - * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid) - */ -#define IS_ADC_TRIGGERED_OVERSAMPLING_MODE(__MODE__) (((__MODE__) == ADC_TRIGGEREDMODE_SINGLE_TRIGGER) || \ - ((__MODE__) == ADC_TRIGGEREDMODE_MULTI_TRIGGER) ) - - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup ADCEx_Exported_Functions - * @{ - */ - -/** @addtogroup ADCEx_Exported_Functions_Group1 - * @{ - */ -/* IO operation functions *****************************************************/ - -/* ADC calibration */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc); -HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor); - -/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ -void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc); -void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc); -void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc); -void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc); - -/** - * @} - */ - -/** @addtogroup ADCEx_Exported_Functions_Group2 - * @{ - */ -/* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc); - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32C0xx_HAL_ADC_EX_H */ diff --git a/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h b/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h deleted file mode 100644 index 40edaef..0000000 --- a/Drivers/STM32C0xx_HAL_Driver/Inc/stm32c0xx_ll_adc.h +++ /dev/null @@ -1,5516 +0,0 @@ -/** - ****************************************************************************** - * @file stm32c0xx_ll_adc.h - * @author MCD Application Team - * @brief Header file of ADC LL module. - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef STM32C0xx_LL_ADC_H -#define STM32C0xx_LL_ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "stm32c0xx.h" - -/** @addtogroup STM32C0xx_LL_Driver - * @{ - */ - -#if defined (ADC1) - -/** @defgroup ADC_LL ADC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup ADC_LL_Private_Constants ADC Private Constants - * @{ - */ - -/* Internal mask for ADC group regular sequencer: */ -/* To select into literal LL_ADC_REG_RANK_x the relevant bits for: */ -/* - sequencer rank bits position into the selected register */ - -#define ADC_REG_RANK_ID_SQRX_MASK (ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0) - -/* Definition of ADC group regular sequencer bits information to be inserted */ -/* into ADC group regular sequencer ranks literals definition. */ -#define ADC_REG_RANK_1_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_SQ1" position in register */ -#define ADC_REG_RANK_2_SQRX_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_SQ2" position in register */ -#define ADC_REG_RANK_3_SQRX_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_SQ3" position in register */ -#define ADC_REG_RANK_4_SQRX_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_SQ4" position in register */ -#define ADC_REG_RANK_5_SQRX_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_SQ5" position in register */ -#define ADC_REG_RANK_6_SQRX_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_SQ6" position in register */ -#define ADC_REG_RANK_7_SQRX_BITOFFSET_POS (24UL) /* Equivalent to bitfield "ADC_CHSELR_SQ7" position in register */ -#define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */ - - -/* Internal mask for ADC group regular trigger: */ -/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ -/* - regular trigger source */ -/* - regular trigger edge */ -#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for - compatibility with some ADC on other STM32 series - having this setting set by HW default value) */ - -/* Mask containing trigger source masks for each of possible */ -/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ -/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \ - ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \ - ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \ - ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) ) - -/* Mask containing trigger edge masks for each of possible */ -/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ -/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) - -/* Definition of ADC group regular trigger bits information. */ -#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */ -#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */ - - -/* Internal mask for ADC channel: */ -/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ -/* - channel identifier defined by number */ -/* - channel identifier defined by bitfield */ -/* - channel differentiation between external channels (connected to */ -/* GPIO pins) and internal channels (connected to internal paths) */ -#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWD1CH) -#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL) -#define ADC_CHANNEL_ID_NUMBER_MASK_SEQ (ADC_CHSELR_SQ1 << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) /* Equivalent to - ADC_CHANNEL_ID_NUMBER_MASK with reduced range: on this STM32 series, ADC group regular sequencer, - if set to mode "fully configurable", can contain channels with a restricted channel number. - Refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */ -#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_CHANNEL_ID_NUMBER_MASK" - position in register */ -#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | \ - ADC_CHANNEL_ID_INTERNAL_CH_MASK) -/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ -#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FUL) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK - >> [Position of bitfield "ADC_CHANNEL_NUMBER_MASK" in register]) */ - -/* Channel differentiation between external and internal channels */ -#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000UL) /* Marker of internal channel */ -#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH) - -/* Definition of channels ID number information to be inserted into */ -/* channels literals definition. */ -#define ADC_CHANNEL_0_NUMBER (0x00000000UL) -#define ADC_CHANNEL_1_NUMBER (ADC_CFGR1_AWD1CH_0) -#define ADC_CHANNEL_2_NUMBER (ADC_CFGR1_AWD1CH_1) -#define ADC_CHANNEL_3_NUMBER (ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) -#define ADC_CHANNEL_4_NUMBER (ADC_CFGR1_AWD1CH_2) -#define ADC_CHANNEL_5_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0) -#define ADC_CHANNEL_6_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1) -#define ADC_CHANNEL_7_NUMBER (ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) -#define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWD1CH_3) -#define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_0) -#define ADC_CHANNEL_10_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1) -#define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) -#define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2) -#define ADC_CHANNEL_13_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0) -#define ADC_CHANNEL_14_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1) -#define ADC_CHANNEL_15_NUMBER (ADC_CFGR1_AWD1CH_3 | ADC_CFGR1_AWD1CH_2 | \ - ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) -#define ADC_CHANNEL_16_NUMBER (ADC_CFGR1_AWD1CH_4) -#define ADC_CHANNEL_17_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_0) -#define ADC_CHANNEL_18_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1) - -#define ADC_CHANNEL_19_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_1 | ADC_CFGR1_AWD1CH_0) -#define ADC_CHANNEL_20_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 ) -#define ADC_CHANNEL_21_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_0) -#define ADC_CHANNEL_22_NUMBER (ADC_CFGR1_AWD1CH_4 | ADC_CFGR1_AWD1CH_2 | ADC_CFGR1_AWD1CH_1) - -/* Definition of channels ID bitfield information to be inserted into */ -/* channels literals definition. */ -#define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0) -#define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1) -#define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2) -#define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3) -#define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4) -#define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5) -#define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6) -#define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7) -#define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8) -#define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9) -#define ADC_CHANNEL_10_BITFIELD (ADC_CHSELR_CHSEL10) -#define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11) -#define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12) -#define ADC_CHANNEL_13_BITFIELD (ADC_CHSELR_CHSEL13) -#define ADC_CHANNEL_14_BITFIELD (ADC_CHSELR_CHSEL14) -#define ADC_CHANNEL_15_BITFIELD (ADC_CHSELR_CHSEL15) -#define ADC_CHANNEL_16_BITFIELD (ADC_CHSELR_CHSEL16) -#define ADC_CHANNEL_17_BITFIELD (ADC_CHSELR_CHSEL17) -#define ADC_CHANNEL_18_BITFIELD (ADC_CHSELR_CHSEL18) -#define ADC_CHANNEL_19_BITFIELD (ADC_CHSELR_CHSEL19) -#define ADC_CHANNEL_20_BITFIELD (ADC_CHSELR_CHSEL20) -#define ADC_CHANNEL_21_BITFIELD (ADC_CHSELR_CHSEL21) -#define ADC_CHANNEL_22_BITFIELD (ADC_CHSELR_CHSEL22) - -/* Internal mask for ADC channel sampling time: */ -/* To select into literals LL_ADC_SAMPLINGTIME_x */ -/* the relevant bits for: */ -/* (concatenation of multiple bits used in register SMPR) */ -/* - ADC channels sampling time: setting channel wise, to map each channel */ -/* on one of the common sampling time available. */ -/* - ADC channels common sampling time: set a sampling time into one of the */ -/* common sampling time available. */ -#define ADC_SAMPLING_TIME_CH_MASK (ADC_CHANNEL_ID_BITFIELD_MASK << ADC_SMPR_SMPSEL0_BITOFFSET_POS) -#define ADC_SAMPLING_TIME_SMP_MASK (ADC_SMPR_SMP2 | ADC_SMPR_SMP1) -#define ADC_SAMPLING_TIME_SMP_SHIFT_MASK (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SMPR_SMP1_BITOFFSET_POS) - -/* Internal mask for ADC analog watchdog: */ -/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ -/* (concatenation of multiple bits used in different analog watchdogs, */ -/* (feature of several watchdogs not available on all STM32 series)). */ -/* - analog watchdog 1: monitored channel defined by number, */ -/* selection of ADC group (ADC group regular). */ -/* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */ -/* selection on groups. */ - -/* Internal register offset for ADC analog watchdog channel configuration */ -#define ADC_AWD_CR1_REGOFFSET (0x00000000UL) -#define ADC_AWD_CR2_REGOFFSET (0x00100000UL) -#define ADC_AWD_CR3_REGOFFSET (0x00200000UL) - -/* Register offset gap between AWD1 and AWD2-AWD3 configuration registers */ -/* (Set separately as ADC_AWD_CRX_REGOFFSET to spare 32 bits space */ -#define ADC_AWD_CR12_REGOFFSETGAP_MASK (ADC_AWD2CR_AWD2CH_0) -#define ADC_AWD_CR12_REGOFFSETGAP_VAL (0x00000024UL) - -#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET | ADC_AWD_CR2_REGOFFSET | ADC_AWD_CR3_REGOFFSET) -#define ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS (20UL) - -#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) -#define ADC_AWD_CR23_CHANNEL_MASK (ADC_AWD2CR_AWD2CH) -#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR23_CHANNEL_MASK) - -#define ADC_AWD_CRX_REGOFFSET_POS (20UL) /* Position of bits ADC_AWD_CRx_REGOFFSET - in ADC_AWD_CRX_REGOFFSET_MASK */ - -/* Internal register offset for ADC analog watchdog threshold configuration */ -#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) -#define ADC_AWD_TR2_REGOFFSET (ADC_AWD_CR2_REGOFFSET) -#define ADC_AWD_TR3_REGOFFSET (ADC_AWD_CR3_REGOFFSET + (1UL << ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS)) -#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET | ADC_AWD_TR2_REGOFFSET | ADC_AWD_TR3_REGOFFSET) -#define ADC_AWD_TRX_REGOFFSET_POS (ADC_AWD_CRX_REGOFFSET_POS) /* Position of bits ADC_SQRx_REGOFFSET - in ADC_AWD_TRX_REGOFFSET_MASK */ -#define ADC_AWD_TRX_BIT_HIGH_MASK (0x00010000UL) /* Selection of 1 bit to discriminate - threshold high: mask of bit */ -#define ADC_AWD_TRX_BIT_HIGH_POS (16UL) /* Selection of 1 bit to discriminate - threshold high: position of bit */ -#define ADC_AWD_TRX_BIT_HIGH_SHIFT4 (ADC_AWD_TRX_BIT_HIGH_POS - 4UL) /* Shift of bit ADC_AWD_TRX_BIT_HIGH to - position to perform a shift of 4 ranks */ -#define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL) - - -/* ADC registers bits positions */ -#define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CFGR1_RES" position in register */ -#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */ -#define ADC_TR1_HT1_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_TR1_HT1" position in register */ -#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL0" position in register */ -#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL1" position in register */ -#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL2" position in register */ -#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL3" position in register */ -#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL4" position in register */ -#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL5" position in register */ -#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL6" position in register */ -#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL7" position in register */ -#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL8" position in register */ -#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL9" position in register */ -#define ADC_CHSELR_CHSEL10_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL10" position in register */ -#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL11" position in register */ -#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL12" position in register */ -#define ADC_CHSELR_CHSEL13_BITOFFSET_POS (13UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL13" position in register */ -#define ADC_CHSELR_CHSEL14_BITOFFSET_POS (14UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL14" position in register */ -#define ADC_CHSELR_CHSEL15_BITOFFSET_POS (15UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL15" position in register */ -#define ADC_CHSELR_CHSEL16_BITOFFSET_POS (16UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL16" position in register */ -#define ADC_CHSELR_CHSEL17_BITOFFSET_POS (17UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL17" position in register */ -#define ADC_CHSELR_CHSEL18_BITOFFSET_POS (18UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL18" position in register */ -#define ADC_CHSELR_CHSEL19_BITOFFSET_POS (19UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL19" position in register */ -#define ADC_CHSELR_CHSEL20_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL20" position in register */ -#define ADC_CHSELR_CHSEL21_BITOFFSET_POS (21UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL21" position in register */ -#define ADC_CHSELR_CHSEL22_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CHSELR_CHSEL22" position in register */ -#define ADC_SMPR_SMP1_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SMPR_SMP1" position in register */ -#define ADC_SMPR_SMP2_BITOFFSET_POS ( 4UL) /* Equivalent to bitfield "ADC_SMPR_SMP2" position in register */ -#define ADC_SMPR_SMPSEL0_BITOFFSET_POS ( 8UL) /* Equivalent to bitfield "ADC_SMPR_SMPSEL0" position in register */ - - -/* ADC registers bits groups */ -#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART \ - | ADC_CR_ADDIS | ADC_CR_ADEN) /* ADC register CR bits with HW property - "rs": Software can read as well as set this bit. Writing '0' has no effect - on the bit value. */ - - -/* ADC internal channels related definitions */ -/* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF756AUL)) /* Internal voltage reference, address of - parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC - (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define VREFINT_CAL_VREF ( 3000UL) /* Analog voltage reference (Vref+) - voltage with which VrefInt has been calibrated in production - (tolerance: +-10 mV) (unit: mV). */ -/* Temperature sensor */ -/* Note: On all devices of series STM32C0, calibration parameter TS_CAL2 is not available. - Therefore, macro "__LL_ADC_CALC_TEMPERATURE()" is not available, - macro "__LL_ADC_CALC_TEMPERATURE_TYP_PARAMS()" must be used and parameter TS_CAL1 can improve accuracy: - replace datasheet parameter of temperature offset (macro argument __TEMPSENSOR_TYP_CALX_V__) - by TEMPSENSOR_CAL1_ADDR - (with taking into account conversion from digital value resolution 12 bit, analog voltage reference ratio - between calibration and application environments) */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF7568UL)) /* Internal temperature sensor, address of - parameter TS_CAL1: On STM32C0, temperature sensor ADC raw data acquired at - temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V - (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at - which temperature sensor has been calibrated in production for data into - TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL_VREFANALOG ( 3000UL) /* Analog voltage reference (Vref+) voltage - with which temperature sensor has been calibrated in production - (tolerance: +-10 mV) (unit: mV). */ - -/** - * @} - */ - - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup ADC_LL_Private_Macros ADC Private Macros - * @{ - */ - -/** - * @brief Driver macro reserved for internal use: set a pointer to - * a register from a register basis from which an offset - * is applied. - * @param __REG__ Register basis from which the offset is applied. - * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). - * @retval Pointer to register address - */ -#define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ - ((__IO uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2UL)))) - -/** - * @} - */ - - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure - * @{ - */ - -/** - * @brief Structure definition of some features of ADC common parameters - * and multimode - * (all ADC instances belonging to the same ADC common instance). - * @note The setting of these parameters by function @ref LL_ADC_CommonInit() - * is conditioned to ADC instances state (all ADC instances - * sharing the same ADC common instance): - * All ADC instances sharing the same ADC common instance must be - * disabled. - */ -typedef struct -{ - uint32_t CommonClock; /*!< Set parameter common to several ADC: Clock source and prescaler. - This parameter can be a value of @ref ADC_LL_EC_COMMON_CLOCK_SOURCE - This feature can be modified afterwards using unitary function - @ref LL_ADC_SetCommonClock(). */ - -} LL_ADC_CommonInitTypeDef; - -/** - * @brief Structure definition of some features of ADC instance. - * @note These parameters have an impact on ADC scope: ADC instance. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Instance . - * @note The setting of these parameters by function @ref LL_ADC_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 series. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - */ -typedef struct -{ - uint32_t Clock; /*!< Set ADC instance clock source and prescaler. - This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE - @note On this STM32 series, this parameter has some clock ratio constraints: - ADC clock synchronous (from PCLK) with prescaler 1 must be enabled - only if PCLK has a 50% duty clock cycle (APB prescaler configured - inside the RCC must be bypassed and the system clock must by 50% duty - cycle). - This feature can be modified afterwards using unitary function - @ref LL_ADC_SetClock(). - For more details, refer to description of this function. */ - - uint32_t Resolution; /*!< Set ADC resolution. - This parameter can be a value of @ref ADC_LL_EC_RESOLUTION - This feature can be modified afterwards using unitary function - @ref LL_ADC_SetResolution(). */ - - uint32_t DataAlignment; /*!< Set ADC conversion data alignment. - This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN - This feature can be modified afterwards using unitary function - @ref LL_ADC_SetDataAlignment(). */ - - uint32_t LowPowerMode; /*!< Set ADC low power mode. - This parameter can be a value of @ref ADC_LL_EC_LP_MODE - This feature can be modified afterwards using unitary function - @ref LL_ADC_SetLowPowerMode(). */ - -} LL_ADC_InitTypeDef; - -/** - * @brief Structure definition of some features of ADC group regular. - * @note These parameters have an impact on ADC scope: ADC group regular. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Group_Regular - * (functions with prefix "REG"). - * @note The setting of these parameters by function @ref LL_ADC_REG_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 series. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - */ -typedef struct -{ - uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or - from external peripheral (timer event, external interrupt line). - This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE - @note On this STM32 series, setting trigger source to external trigger also - set trigger polarity to rising edge(default setting for compatibility - with some ADC on other STM32 series having this setting set by HW - default value). - In case of need to modify trigger edge, use function - @ref LL_ADC_REG_SetTriggerEdge(). - This feature can be modified afterwards using unitary function - @ref LL_ADC_REG_SetTriggerSource(). */ - - uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. - @note This parameter has an effect only if group regular sequencer is set - to mode "fully configurable". Refer to function - @ref LL_ADC_REG_SetSequencerConfigurable(). - This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH - This feature can be modified afterwards using unitary function - @ref LL_ADC_REG_SetSequencerLength(). */ - - uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided - and scan conversions interrupted every selected number of ranks. - This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE - @note This parameter has an effect only if group regular sequencer is - enabled (depending on the sequencer mode: scan length of 2 ranks or - more, or several ADC channels enabled in group regular sequencer. - Refer to function @ref LL_ADC_REG_SetSequencerConfigurable() ). - This feature can be modified afterwards using unitary function - @ref LL_ADC_REG_SetSequencerDiscont(). */ - - uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC - conversions are performed in single mode (one conversion per trigger) or in - continuous mode (after the first trigger, following conversions launched - successively automatically). - This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE - Note: It is not possible to enable both ADC group regular continuous mode - and discontinuous mode. - This feature can be modified afterwards using unitary function - @ref LL_ADC_REG_SetContinuousMode(). */ - - uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer - by DMA, and DMA requests mode. - This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER - This feature can be modified afterwards using unitary function - @ref LL_ADC_REG_SetDMATransfer(). */ - - uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: - data preserved or overwritten. - This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR - This feature can be modified afterwards using unitary function - @ref LL_ADC_REG_SetOverrun(). */ - -} LL_ADC_REG_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants - * @{ - */ - -/** @defgroup ADC_LL_EC_FLAG ADC flags - * @brief Flags defines which can be used with LL_ADC_ReadReg function - * @{ - */ -#define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */ -#define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC flag ADC channel configuration ready */ -#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary - conversion */ -#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence - conversions */ -#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ -#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ -#define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ -#define LL_ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC flag ADC analog watchdog 2 */ -#define LL_ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC flag ADC analog watchdog 3 */ -#define LL_ADC_FLAG_EOCAL ADC_ISR_EOCAL /*!< ADC flag end of calibration */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) - * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions - * @{ - */ -#define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */ -#define LL_ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC interruption channel configuration ready */ -#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary - conversion */ -#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence - conversions */ -#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */ -#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling - phase */ -#define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */ -#define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */ -#define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */ -#define LL_ADC_IT_EOCAL ADC_IER_EOCALIE /*!< ADC interruption ADC end of calibration */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose - * @{ - */ -/* List of ADC registers intended to be used (most commonly) with */ -/* DMA transfer. */ -/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ -#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register - (corresponding to register DR) to be used with ADC configured in independent - mode. Without DMA transfer, register accessed by LL function - @ref LL_ADC_REG_ReadConversionData32() and other - functions @ref LL_ADC_REG_ReadConversionDatax() */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source - * @{ - */ -#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without - prescaler */ -#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with - prescaler division by 2. Setting common to ADC instances of ADC common - group, applied ADC instance wise to each instance clock set to clock source - asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with - prescaler division by 4. Setting common to ADC instances of ADC common - group, applied ADC instance wise to each instance clock set to clock source - asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with - prescaler division by 6. Setting common to ADC instances of ADC common - group, applied ADC instance wise to each instance clock set to clock source - asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with - prescaler division by 8. Setting common to ADC instances of ADC common - group, applied ADC instance wise to each instance clock set to clock source - asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with - prescaler division by 10. Setting common to ADC instances of ADC common - group, applied ADC instance wise to each instance clock set to clock source - asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with - prescaler division by 12. Setting common to ADC instances of ADC common - group, applied ADC instance wise to each instance clock set to clock source - asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \ - | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with - prescaler division by 16. Setting common to ADC instances of ADC common - group, applied ADC instance wise to each instance clock set to clock source - asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with - prescaler division by 32. Setting common to ADC instances of ADC common - group, applied ADC instance wise to each instance clock set to clock source - asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with - prescaler division by 64. Setting common to ADC instances of ADC common - group, applied ADC instance wise to each instance clock set to clock source - asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with - prescaler division by 128. Setting common to ADC instances of ADC common - group, applied ADC instance wise to each instance clock set to clock source - asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \ - | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with - prescaler division by 256. Setting common to ADC instances of ADC common - group, applied ADC instance wise to each instance clock set to clock source - asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels - * @{ - */ -/* Note: Other measurement paths to internal channels may be available */ -/* (connections to other peripherals). */ -/* If they are not listed below, they do not require any specific */ -/* path enable. In this case, Access to measurement path is done */ -/* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ -#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ -#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel - temperature sensor */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source - * @{ - */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock - divided by 4 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock - divided by 2 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 \ - | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock - not divided */ -#define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock - prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution - * @{ - */ -#define LL_ADC_RESOLUTION_12B (0x00000000UL) /*!< ADC resolution 12 bits */ -#define LL_ADC_RESOLUTION_10B ( ADC_CFGR1_RES_0) /*!< ADC resolution 10 bits */ -#define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RES_1 ) /*!< ADC resolution 8 bits */ -#define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RES_1 | ADC_CFGR1_RES_0) /*!< ADC resolution 6 bits */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment - * @{ - */ -#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned - (alignment on data register LSB bit 0)*/ -#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned - (alignment on data register MSB bit 15)*/ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode - * @{ - */ -#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ -#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power - mode, ADC conversions are performed only when necessary - (when previous ADC conversion data is read). - See description with function @ref LL_ADC_SetLowPowerMode(). */ -#define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC - automatically powers-off after a ADC conversion and automatically wakes up - when a new ADC conversion is triggered (with startup time between trigger - and start of sampling). See description with function - @ref LL_ADC_SetLowPowerMode(). */ -#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait -and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode - * @{ - */ -#define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. - Note: ADC trigger frequency mode must be set to low frequency when a duration - is exceeded before ADC conversion start trigger event (between ADC enable - and ADC conversion start trigger event or between two ADC conversion start - trigger event). - Duration value: Refer to device datasheet, parameter "tIdle". */ -#define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. - Note: ADC trigger frequency mode must be set to low frequency when a duration - is exceeded before ADC conversion start trigger event (between ADC enable - and ADC conversion start trigger event or between two ADC conversion start - trigger event). - Duration value: Refer to device datasheet, parameter "tIdle". */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_COMMON_CLOCK_FREQ_MODE ADC common - Clock frequency mode - * @{ - */ -#define LL_ADC_CLOCK_FREQ_MODE_HIGH LL_ADC_TRIGGER_FREQ_HIGH /*!< LL ADC define maintained for legacy purpose */ -#define LL_ADC_CLOCK_FREQ_MODE_LOW LL_ADC_TRIGGER_FREQ_LOW /*!< LL ADC define maintained for legacy purpose */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels - * @{ - */ -#define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group - of channels: sampling time nb 1 */ -#define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS \ - | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group - of channels: sampling time nb 2 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups - * @{ - */ -#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number - * @{ - */ -#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \ - | ADC_CHANNEL_0_BITFIELD ) /*!< ADC channel ADCx_IN0 */ -#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \ - | ADC_CHANNEL_1_BITFIELD ) /*!< ADC channel ADCx_IN1 */ -#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \ - | ADC_CHANNEL_2_BITFIELD ) /*!< ADC channel ADCx_IN2 */ -#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \ - | ADC_CHANNEL_3_BITFIELD ) /*!< ADC channel ADCx_IN3 */ -#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \ - | ADC_CHANNEL_4_BITFIELD ) /*!< ADC channel ADCx_IN4 */ -#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \ - | ADC_CHANNEL_5_BITFIELD ) /*!< ADC channel ADCx_IN5 */ -#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \ - | ADC_CHANNEL_6_BITFIELD ) /*!< ADC channel ADCx_IN6 */ -#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \ - | ADC_CHANNEL_7_BITFIELD ) /*!< ADC channel ADCx_IN7 */ -#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \ - | ADC_CHANNEL_8_BITFIELD ) /*!< ADC channel ADCx_IN8 */ -#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \ - | ADC_CHANNEL_9_BITFIELD ) /*!< ADC channel ADCx_IN9 */ -#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \ - | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */ -#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \ - | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */ -#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \ - | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */ -#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \ - | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */ -#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \ - | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */ -#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \ - | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */ -#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \ - | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */ -#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \ - | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */ -#define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER \ - | ADC_CHANNEL_18_BITFIELD) /*!< ADC channel ADCx_IN18 */ -#define LL_ADC_CHANNEL_19 (ADC_CHANNEL_19_NUMBER \ - | ADC_CHANNEL_19_BITFIELD) /*!< ADC channel ADCx_IN19 */ -#define LL_ADC_CHANNEL_20 (ADC_CHANNEL_20_NUMBER \ - | ADC_CHANNEL_20_BITFIELD) /*!< ADC channel ADCx_IN20 */ -#define LL_ADC_CHANNEL_21 (ADC_CHANNEL_21_NUMBER \ - | ADC_CHANNEL_21_BITFIELD) /*!< ADC channel ADCx_IN21 */ -#define LL_ADC_CHANNEL_22 (ADC_CHANNEL_22_NUMBER \ - | ADC_CHANNEL_22_BITFIELD) /*!< ADC channel ADCx_IN22 */ -#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_10 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel - connected to VrefInt: Internal voltage reference. */ -#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_9 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel - connected to Temperature sensor. */ -#define LL_ADC_CHANNEL_VDDA (LL_ADC_CHANNEL_15 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel - connected to VDDA. */ -#define LL_ADC_CHANNEL_VSSA (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel - connected to VSSA. */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source - * @{ - */ -#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start */ -#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger - from external peripheral: TIM1 TRGO. - Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular - conversion trigger from external peripheral: - TIM1 channel 4 event (capture compare: input capture or output capture). - Trigger edge set to rising edge (default setting). */ -#if defined(TIM2) -#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular - conversion trigger from external peripheral: TIM2 TRGO. - Trigger edge set to rising edge (default setting). */ -#endif /* TIM2 */ -#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \ - | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger - from external peripheral: TIM3 TRGO. - Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \ - | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular - conversion trigger from external peripheral: external interrupt line 11. - Trigger edge set to rising edge (default setting). */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge - * @{ - */ -#define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion - trigger polarity set to rising edge */ -#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1) /*!< ADC group regular conversion - trigger polarity set to falling edge */ -#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion - trigger polarity set to both rising and falling edges */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode - * @{ - */ -#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode: - one conversion per trigger */ -#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions performed in continuous mode: - after the first trigger, following conversions launched successively - automatically */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data - * @{ - */ -#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */ -#define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, - in limited mode (one shot mode): DMA transfer requests are stopped when - number of DMA data transfers (number of ADC conversions) is reached. - This ADC mode is intended to be used with DMA mode non-circular. */ -#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are - transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, - whatever number of DMA data transferred (number of ADC conversions). - This ADC mode is intended to be used with DMA mode circular. */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data - * @{ - */ -#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: - data preserved */ -#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: - data overwritten */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility - * @{ - */ -#define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable: - sequencer length and each rank affectation to a channel are fixed - by channel HW number. Refer to description of function - @ref LL_ADC_REG_SetSequencerChannels(). */ -#define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable: - sequencer length and each rank affectation to a channel are configurable. - Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length - * @{ - */ -#define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable - (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable - with 2 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable - with 3 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable - with 4 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable - with 5 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable - with 6 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable - with 7 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable - with 8 ranks in the sequence */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction - * @{ - */ -#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only if - sequencer set to mode not fully configurable, refer to function - @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan - direction forward: from lowest channel number to highest channel number - (scan of all ranks, ADC conversion of ranks with channels enabled in - sequencer). On some other STM32 series, this setting is not available - and the default scan direction is forward. */ -#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only if - sequencer set to mode not fully configurable, refer to function - @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan - direction backward: from highest channel number to lowest channel number - (scan of all ranks, ADC conversion of ranks with channels enabled in - sequencer) */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode - * @{ - */ -#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer - discontinuous mode disable */ -#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer - discontinuous mode enable with sequence interruption every rank */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks - * @{ - */ -#define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 1 */ -#define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 2 */ -#define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 3 */ -#define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 4 */ -#define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 5 */ -#define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 6 */ -#define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 7 */ -#define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 8 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time - * @{ - */ -#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */ -#define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 \ - | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 \ - | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 \ - | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 \ - | ADC_SMPR_SMP1_1 \ - | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number - * @{ - */ -#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \ - | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ -#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \ - | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ -#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \ - | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels - * @{ - */ -#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring - disabled */ -#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \ - | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring - of all channels, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN0, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN1, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN2, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN3, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN4, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN5, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN6, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN7, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN8, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN9, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN10, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN11, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN12, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN13, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN14, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN15, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN16, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN17, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_18_REG ((LL_ADC_CHANNEL_18 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN18, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_19_REG ((LL_ADC_CHANNEL_19 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN19, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_20_REG ((LL_ADC_CHANNEL_20 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN20, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_21_REG ((LL_ADC_CHANNEL_21 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN21, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_22_REG ((LL_ADC_CHANNEL_22 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC channel ADCx_IN22, converted by group regular only */ -#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC internal channel connected to VrefInt: Internal voltage reference, - converted by group regular only */ -#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC internal channel connected to Temperature sensor, - converted by group regular only */ -#define LL_ADC_AWD_CH_VSSA_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC internal channel connected to VSSA : internal analog supply ground, - converted by group regular only */ -#define LL_ADC_AWD_CH_VDDA_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ - | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring - of ADC internal channel connected to VDDA : internal analog power supply, - converted by group regular only */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds - * @{ - */ -#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1) /*!< ADC analog watchdog threshold high */ -#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */ -#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 \ - | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low - concatenated into the same data */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope - * @{ - */ -#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ -#define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of - ADC group regular. Literal suffix "continued" is kept for compatibility - with other STM32 devices featuring ADC group injected, in this case other - oversampling scope parameters are available. */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode - * @{ - */ -#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode -(all conversions of oversampling ratio are done from 1 trigger) */ -#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous - mode (each conversion of oversampling ratio needs a trigger) */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio - * @{ - */ -#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 - (sum of conversions data computed to result as oversampling conversion data - (before potential shift) */ -#define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 - (sum of conversions data computed to result as oversampling conversion data - (before potential shift) */ -#define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8 - (sum of conversions data computed to result as oversampling conversion data - (before potential shift) */ -#define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 - (sum of conversions data computed to result as oversampling conversion data - (before potential shift) */ -#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32 - (sum of conversions data computed to result as oversampling conversion data - (before potential shift) */ -#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 - (sum of conversions data computed to result as oversampling conversion data - (before potential shift) */ -#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128 - (sum of conversions data computed to result as oversampling conversion data - (before potential shift) */ -#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \ - | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 - (sum of conversions data computed to result as oversampling conversion data - (before potential shift) */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift - * @{ - */ -#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift - (sum of the ADC conversions data is not divided to result as oversampling - conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1 - (sum of the ADC conversions data (after OVS ratio) is divided by 2 - to result as oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2 - (sum of the ADC conversions data (after OVS ratio) is divided by 4 - to result as oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3 - (sum of the ADC conversions data (after OVS ratio) is divided by 8 - to result as oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4 - (sum of the ADC conversions data (after OVS ratio) is divided by 16 - to result as oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5 - (sum of the ADC conversions data (after OVS ratio) is divided by 32 - to result as oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6 - (sum of the ADC conversions data (after OVS ratio) is divided by 64 - to result as oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \ - | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7 - (sum of the ADC conversions data (after OVS ratio) is divided by 128 - to result as oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8 - (sum of the ADC conversions data (after OVS ratio) is divided by 256 - to result as oversampling conversion data) */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_HELPER_MACRO Definitions of constants used by helper macro - * @{ - */ -#define LL_ADC_TEMPERATURE_CALC_ERROR ((int16_t)0x7FFF) /* Temperature calculation error using helper macro - @ref __LL_ADC_CALC_TEMPERATURE(), due to issue on - calibration parameters. This value is coded on 16 bits - (to fit on signed word or double word) and corresponds - to an inconsistent temperature value. */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays - * @note Only ADC peripheral HW delays are defined in ADC LL driver driver, - * not timeout values. - * For details on delays values, refer to descriptions in source code - * above each literal definition. - * @{ - */ - -/* Note: Only ADC peripheral HW delays are defined in ADC LL driver driver, */ -/* not timeout values. */ -/* Timeout values for ADC operations are dependent to device clock */ -/* configuration (system clock versus ADC clock), */ -/* and therefore must be defined in user application. */ -/* Indications for estimation of ADC timeout delays, for this */ -/* STM32 series: */ -/* - ADC calibration time: maximum delay is 82/fADC. */ -/* (refer to device datasheet, parameter "tCAL") */ -/* - ADC enable time: maximum delay is 1 conversion cycle. */ -/* (refer to device datasheet, parameter "tSTAB") */ -/* - ADC disable time: maximum delay should be a few ADC clock cycles */ -/* - ADC stop conversion time: maximum delay should be a few ADC clock */ -/* cycles */ -/* - ADC conversion time: duration depending on ADC clock and ADC */ -/* configuration. */ -/* (refer to device reference manual, section "Timing") */ - -/* Delay for ADC stabilization time (ADC voltage regulator start-up time) */ -/* Delay set to maximum value (refer to device datasheet, */ -/* parameter "tADCVREG_STUP"). */ -/* Unit: us */ -#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage - regulator start-up time) */ - -/* Delay for internal voltage reference stabilization time. */ -/* Delay set to maximum value (refer to device datasheet, */ -/* parameter "tstart_vrefint"). */ -/* Unit: us */ -#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization - time */ - -/* Delay for temperature sensor stabilization time. */ -/* Literal set to maximum value (refer to device datasheet, */ -/* parameter "tSTART"). */ -/* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time - (starting from temperature sensor enable, refer to - @ref LL_ADC_SetCommonPathInternalCh()) */ -#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization - time (starting from ADC enable, refer to - @ref LL_ADC_Enable()) */ - -/* Delay required between ADC end of calibration and ADC enable. */ -/* Note: On this STM32 series, a minimum number of ADC clock cycles */ -/* are required between ADC end of calibration and ADC enable. */ -/* Wait time can be computed in user application by waiting for the */ -/* equivalent number of CPU cycles, by taking into account */ -/* ratio of CPU clock versus ADC clock prescalers. */ -/* Unit: ADC clock cycles. */ -#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL) /*!< Delay required between ADC end of calibration - and ADC enable */ - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros - * @{ - */ - -/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in ADC register - * @param __INSTANCE__ ADC Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in ADC register - * @param __INSTANCE__ ADC Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro - * @{ - */ - -/** - * @brief Helper macro to get ADC channel number in decimal format - * from literals LL_ADC_CHANNEL_x. - * @note Example: - * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) - * will return decimal number "4". - * @note The input can be a value from functions where a channel - * number is returned, either defined with number - * or with bitfield (only one bit must be set). - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - * @retval Value between Min_Data=0 and Max_Data=18 - */ -#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0UL) ? \ - ( \ - ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ - ) \ - : \ - ((((__CHANNEL__) & ADC_CHANNEL_0_BITFIELD) == ADC_CHANNEL_0_BITFIELD) ? (0UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_1_BITFIELD) == ADC_CHANNEL_1_BITFIELD) ? (1UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_2_BITFIELD) == ADC_CHANNEL_2_BITFIELD) ? (2UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_3_BITFIELD) == ADC_CHANNEL_3_BITFIELD) ? (3UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_4_BITFIELD) == ADC_CHANNEL_4_BITFIELD) ? (4UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_5_BITFIELD) == ADC_CHANNEL_5_BITFIELD) ? (5UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_6_BITFIELD) == ADC_CHANNEL_6_BITFIELD) ? (6UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_7_BITFIELD) == ADC_CHANNEL_7_BITFIELD) ? (7UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_8_BITFIELD) == ADC_CHANNEL_8_BITFIELD) ? (8UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_9_BITFIELD) == ADC_CHANNEL_9_BITFIELD) ? (9UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_10_BITFIELD) == ADC_CHANNEL_10_BITFIELD) ? (10UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_11_BITFIELD) == ADC_CHANNEL_11_BITFIELD) ? (11UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_12_BITFIELD) == ADC_CHANNEL_12_BITFIELD) ? (12UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_13_BITFIELD) == ADC_CHANNEL_13_BITFIELD) ? (13UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_14_BITFIELD) == ADC_CHANNEL_14_BITFIELD) ? (14UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_15_BITFIELD) == ADC_CHANNEL_15_BITFIELD) ? (15UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_16_BITFIELD) == ADC_CHANNEL_16_BITFIELD) ? (16UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_17_BITFIELD) == ADC_CHANNEL_17_BITFIELD) ? (17UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_18_BITFIELD) == ADC_CHANNEL_18_BITFIELD) ? (18UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_19_BITFIELD) == ADC_CHANNEL_19_BITFIELD) ? (19UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_20_BITFIELD) == ADC_CHANNEL_20_BITFIELD) ? (20UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_21_BITFIELD) == ADC_CHANNEL_21_BITFIELD) ? (21UL) : \ - ((((__CHANNEL__) & ADC_CHANNEL_22_BITFIELD) == ADC_CHANNEL_22_BITFIELD) ? (22UL) : \ - (0UL))))))))))))))))))))))))) - -/** - * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x - * from number in decimal format. - * @note Example: - * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) - * will return a data equivalent to "LL_ADC_CHANNEL_4". - * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 - * @retval Returned value can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - */ -#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__))) - -/** - * @brief Helper macro to determine whether the selected channel - * corresponds to literal definitions of driver. - * @note The different literal definitions of ADC channels are: - * - ADC internal channel: - * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... - * - ADC external channel (channel connected to a GPIO pin): - * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... - * @note The channel parameter must be a value defined from literal - * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, - * LL_ADC_CHANNEL_TEMPSENSOR, ...), - * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), - * must not be a value from functions where a channel number is - * returned from ADC registers, - * because internal and external channels share the same channel - * number in ADC registers. The differentiation is made only with - * parameters definitions of driver. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel - * (channel connected to a GPIO pin). - * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. - */ -#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ - (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0UL) - -/** - * @brief Helper macro to convert a channel defined from parameter - * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, - * LL_ADC_CHANNEL_TEMPSENSOR, ...), - * to its equivalent parameter definition of a ADC external channel - * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). - * @note The channel parameter can be, additionally to a value - * defined from parameter definition of a ADC internal channel - * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), - * a value defined from parameter definition of - * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) - * or a value from functions where a channel number is returned - * from ADC registers. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_13 - * @arg @ref LL_ADC_CHANNEL_14 - * @arg @ref LL_ADC_CHANNEL_15 - * @arg @ref LL_ADC_CHANNEL_16 - * @arg @ref LL_ADC_CHANNEL_17 - * @arg @ref LL_ADC_CHANNEL_18 - * @arg @ref LL_ADC_CHANNEL_19 - * @arg @ref LL_ADC_CHANNEL_20 - * @arg @ref LL_ADC_CHANNEL_21 - * @arg @ref LL_ADC_CHANNEL_22 - */ -#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ - ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) - -/** - * @brief Helper macro to determine whether the internal channel - * selected is available on the ADC instance selected. - * @note The channel parameter must be a value defined from parameter - * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, - * LL_ADC_CHANNEL_TEMPSENSOR, ...), - * must not be a value defined from parameter definition of - * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) - * or a value from functions where a channel number is - * returned from ADC registers, - * because internal and external channels share the same channel - * number in ADC registers. The differentiation is made only with - * parameters definitions of driver. - * @param __ADC_INSTANCE__ ADC instance - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_VREFINT - * @arg @ref ADC_CHANNEL_TEMPSENSOR - * @arg @ref ADC_CHANNEL_VDDA - * @arg @ref ADC_CHANNEL_VSSA - * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. - * Value "1" if the internal channel selected is available on the ADC instance selected. - */ -#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ - (((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VDDA) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VSSA)) - -/** - * @brief Helper macro to define ADC analog watchdog parameter: - * define a single channel to monitor with analog watchdog - * from sequencer channel and groups definition. - * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). - * Example: - * LL_ADC_SetAnalogWDMonitChannels( - * ADC1, LL_ADC_AWD1, - * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - * @param __GROUP__ This parameter can be one of the following values: - * @arg @ref LL_ADC_GROUP_REGULAR - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_AWD_DISABLE - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1) - * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (1) - * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (1) - * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (1) - * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1) - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG - * @arg @ref LL_ADC_AWD_CH_VDDA_REG - * @arg @ref LL_ADC_AWD_CH_VSSA_REG - * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx. - */ -#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__) \ - (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) - -/** - * @brief Helper macro to set the value of ADC analog watchdog threshold high - * or low in function of ADC resolution, when ADC resolution is - * different of 12 bits. - * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds() - * or @ref LL_ADC_SetAnalogWDThresholds(). - * Example, with a ADC resolution of 8 bits, to set the value of - * analog watchdog threshold high (on 8 bits): - * LL_ADC_SetAnalogWDThresholds - * (< ADCx param >, - * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) - * ); - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ - ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U ))) - -/** - * @brief Helper macro to get the value of ADC analog watchdog threshold high - * or low in function of ADC resolution, when ADC resolution is - * different of 12 bits. - * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). - * Example, with a ADC resolution of 8 bits, to get the value of - * analog watchdog threshold high (on 8 bits): - * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION - * (LL_ADC_RESOLUTION_8B, - * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) - * ); - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ - ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U ))) - -/** - * @brief Helper macro to get the ADC analog watchdog threshold high - * or low from raw value containing both thresholds concatenated. - * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). - * Example, to get analog watchdog threshold high from the register raw value: - * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, ); - * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH - * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ - (((__AWD_THRESHOLDS__) >> (((__AWD_THRESHOLD_TYPE__) & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)) \ - & LL_ADC_AWD_THRESHOLD_LOW) - -/** - * @brief Helper macro to select the ADC common instance - * to which is belonging the selected ADC instance. - * @note ADC common register instance can be used for: - * - Set parameters common to several ADC instances - * - Multimode (for devices with several ADC instances) - * Refer to functions having argument "ADCxy_COMMON" as parameter. - * @param __ADCx__ ADC instance - * @retval ADC common register instance - */ -#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ - (ADC1_COMMON) - -/** - * @brief Helper macro to check if all ADC instances sharing the same - * ADC common instance are disabled. - * @note This check is required by functions with setting conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * Refer to functions having argument "ADCxy_COMMON" as parameter. - * @note On devices with only 1 ADC common instance, parameter of this macro - * is useless and can be ignored (parameter kept for compatibility - * with devices featuring several ADC common instances). - * @param __ADCXY_COMMON__ ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Value "0" if all ADC instances sharing the same ADC common instance - * are disabled. - * Value "1" if at least one ADC instance sharing the same ADC common instance - * is enabled. - */ -#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - LL_ADC_IsEnabled(ADC1) - -/** - * @brief Helper macro to define the ADC conversion data full-scale digital - * value corresponding to the selected ADC resolution. - * @note ADC conversion data full-scale corresponds to voltage range - * determined by analog voltage references Vref+ and Vref- - * (refer to reference manual). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval ADC conversion data full-scale digital value (unit: digital value of ADC conversion data) - */ -#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - (0xFFFUL >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL))) - -/** - * @brief Helper macro to convert the ADC conversion data from - * a resolution to another resolution. - * @param __DATA__ ADC conversion data to be converted - * @param __ADC_RESOLUTION_CURRENT__ Resolution of the data to be converted - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval ADC conversion data to the requested resolution - */ -#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ - __ADC_RESOLUTION_CURRENT__,\ - __ADC_RESOLUTION_TARGET__) \ -(((__DATA__) \ - << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL))) \ - >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1UL)) \ -) - -/** - * @brief Helper macro to calculate the voltage (unit: mVolt) - * corresponding to a ADC conversion data (unit: digital value). - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) - * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) - * (unit: digital value). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval ADC conversion data equivalent voltage value (unit: mVolt) - */ -#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ - __ADC_DATA__,\ - __ADC_RESOLUTION__) \ -((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ -) - -/** - * @brief Helper macro to calculate analog reference voltage (Vref+) - * (unit: mVolt) from ADC conversion data of internal voltage - * reference VrefInt. - * @note Computation is using VrefInt calibration value - * stored in system memory for each device during production. - * @note This voltage depends on user board environment: voltage level - * connected to pin Vref+. - * On devices with small package, the pin Vref+ is not present - * and internally bonded to pin Vdda. - * @note On this STM32 series, calibration data of internal voltage reference - * VrefInt corresponds to a resolution of 12 bits, - * this is the recommended ADC resolution to convert voltage of - * internal voltage reference VrefInt. - * Otherwise, this macro performs the processing to scale - * ADC conversion data to 12 bits. - * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) - * of internal voltage reference VrefInt (unit: digital value). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval Analog reference voltage (unit: mV) - */ -#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ - __ADC_RESOLUTION__) \ -(((uint32_t)(*VREFINT_CAL_ADDR) * VREFINT_CAL_VREF) \ - / __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B) \ -) - -/** - * @brief Helper macro to calculate the temperature (unit: degree Celsius) - * from ADC conversion data of internal temperature sensor. - * @note Computation is using temperature sensor typical values - * (refer to device datasheet). - * @note Calculation formula: - * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) - * / Avg_Slope + CALx_TEMP - * with TS_ADC_DATA = temperature sensor raw data measured by ADC - * (unit: digital value) - * Avg_Slope = temperature sensor slope - * (unit: uV/Degree Celsius) - * TS_TYP_CALx_VOLT = temperature sensor digital value at - * temperature CALx_TEMP (unit: mV) - * Caution: Calculation relevancy under reserve the temperature sensor - * of the current device has characteristics in line with - * datasheet typical values. - * @note: On this STM32 series, calibtation parameter TS_CAL1 can be used - * to improve calculation accuracy. - * Refer to @ref TEMPSENSOR_CAL1_ADDR. - * @note As calculation input, the analog reference voltage (Vref+) must be - * defined as it impacts the ADC LSB equivalent voltage. - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note ADC measurement data must correspond to a resolution of 12 bits - * (full scale digital value 4095). If not the case, the data must be - * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value - (unit: uV/DegCelsius). - * On this STM32 series, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value - (at temperature and Vref+ defined in parameters below) (unit: mV). - * On this STM32 series, refer to datasheet parameter "V30" (corresponding - * to TS_CAL1). - * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage - (see parameter above) is corresponding (unit: mV) - * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV) - * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). - * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval Temperature (unit: degree Celsius) - */ -#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ - __TEMPSENSOR_TYP_CALX_V__,\ - __TEMPSENSOR_CALX_TEMP__,\ - __VREFANALOG_VOLTAGE__,\ - __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ -(((((int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ - * 1000UL) \ - - \ - (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ - * 1000UL) \ - ) \ - ) / (int32_t)(__TEMPSENSOR_TYP_AVGSLOPE__) \ - ) + (int32_t)(__TEMPSENSOR_CALX_TEMP__) \ -) - -/** - * @} - */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions - * @{ - */ - -/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management - * @{ - */ -/* Note: LL ADC functions to set DMA transfer are located into sections of */ -/* configuration of ADC instance, groups and multimode (if available): */ -/* @ref LL_ADC_REG_SetDMATransfer(), ... */ - -/** - * @brief Function to help to configure DMA transfer from ADC: retrieve the - * ADC register address from ADC instance and a list of ADC registers - * intended to be used (most commonly) with DMA transfer. - * @note These ADC registers are data registers: - * when ADC conversion data is available in ADC data registers, - * ADC generates a DMA transfer request. - * @note This macro is intended to be used with LL DMA driver, refer to - * function "LL_DMA_ConfigAddresses()". - * Example: - * LL_DMA_ConfigAddresses(DMA1, - * LL_DMA_CHANNEL_1, - * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), - * (uint32_t)&< array or variable >, - * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); - * @note For devices with several ADC: in multimode, some devices - * use a different data register outside of ADC instance scope - * (common data register). This macro manages this register difference, - * only ADC instance has to be set as parameter. - * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr - * @param ADCx ADC instance - * @param Register This parameter can be one of the following values: - * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA - * @retval ADC register address - */ -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) -{ - /* Prevent unused argument(s) compilation warning */ - (void)(Register); - - /* Retrieve address of register DR */ - return (uint32_t) &(ADCx->DR); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several - * ADC instances - * @{ - */ - -/** - * @brief Set parameter common to several ADC: Clock source and prescaler. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * This check can be done with function @ref LL_ADC_IsEnabled() for each - * ADC instance or by using helper macro helper macro - * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR PRESC LL_ADC_SetCommonClock - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param CommonClock This parameter can be one of the following values: - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1) - * - * (1) ADC common clock asynchronous prescaler is applied to - * each ADC instance if the corresponding ADC instance clock - * is set to clock source asynchronous. - * (refer to function @ref LL_ADC_SetClock() ). - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t CommonClock) -{ - MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_PRESC, CommonClock); -} - -/** - * @brief Get parameter common to several ADC: Clock source and prescaler. - * @rmtoll CCR PRESC LL_ADC_GetCommonClock - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV1 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV2 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV4 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV6 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV8 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV10 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV12 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV16 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV32 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV64 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV128 (1) - * @arg @ref LL_ADC_CLOCK_ASYNC_DIV256 (1) - * - * (1) ADC common clock asynchronous prescaler is applied to - * each ADC instance if the corresponding ADC instance clock - * is set to clock source asynchronous. - * (refer to function @ref LL_ADC_SetClock() ). - */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC)); -} - -/** - * @brief Set parameter common to several ADC: measurement path to - * internal channels (VrefInt, temperature sensor, ...). - * Configure all paths (overwrite current configuration). - * @note One or several values can be selected. - * Example: (LL_ADC_PATH_INTERNAL_VREFINT | - * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * The values not selected are removed from configuration. - * @note Stabilization time of measurement path to internal channel: - * After enabling internal paths, before starting ADC conversion, - * a delay is required for internal voltage reference and - * temperature sensor stabilization time. - * Refer to device datasheet. - * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. - * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US, - * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US. - * @note ADC internal channel sampling time constraint: - * For ADC conversion of internal channels, - * a sampling time minimum value is required. - * Refer to device datasheet. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * This check can be done with function @ref LL_ADC_IsEnabled() for each - * ADC instance or by using helper macro helper macro - * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n - * CCR TSEN LL_ADC_SetCommonPathInternalCh\n - * CCR VBATEN LL_ADC_SetCommonPathInternalCh - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param PathInternal This parameter can be a combination of the following values: - * @arg @ref LL_ADC_PATH_INTERNAL_NONE - * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT - * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) -{ - MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal); -} - -/** - * @brief Set parameter common to several ADC: measurement path to - * internal channels (VrefInt, temperature sensor, ...). - * Add paths to the current configuration. - * @note One or several values can be selected. - * Example: (LL_ADC_PATH_INTERNAL_VREFINT | - * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * @note Stabilization time of measurement path to internal channel: - * After enabling internal paths, before starting ADC conversion, - * a delay is required for internal voltage reference and - * temperature sensor stabilization time. - * Refer to device datasheet. - * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. - * Refer to literals @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US, - * @ref LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US. - * @note ADC internal channel sampling time constraint: - * For ADC conversion of internal channels, - * a sampling time minimum value is required. - * Refer to device datasheet. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * This check can be done with function @ref LL_ADC_IsEnabled() for each - * ADC instance or by using helper macro helper macro - * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChAdd\n - * CCR TSEN LL_ADC_SetCommonPathInternalChAdd\n - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param PathInternal This parameter can be a combination of the following values: - * @arg @ref LL_ADC_PATH_INTERNAL_NONE - * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT - * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCommonPathInternalChAdd(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) -{ - SET_BIT(ADCxy_COMMON->CCR, PathInternal); -} - -/** - * @brief Set parameter common to several ADC: measurement path to - * internal channels (VrefInt, temperature sensor, ...). - * Remove paths to the current configuration. - * @note One or several values can be selected. - * Example: (LL_ADC_PATH_INTERNAL_VREFINT | - * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * This check can be done with function @ref LL_ADC_IsEnabled() for each - * ADC instance or by using helper macro helper macro - * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalChRem\n - * CCR TSEN LL_ADC_SetCommonPathInternalChRem\n - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param PathInternal This parameter can be a combination of the following values: - * @arg @ref LL_ADC_PATH_INTERNAL_NONE - * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT - * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) -{ - CLEAR_BIT(ADCxy_COMMON->CCR, PathInternal); -} - -/** - * @brief Get parameter common to several ADC: measurement path to internal - * channels (VrefInt, temperature sensor, ...). - * @note One or several values can be selected. - * Example: (LL_ADC_PATH_INTERNAL_VREFINT | - * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n - * CCR TSEN LL_ADC_GetCommonPathInternalCh\n - * CCR VBATEN LL_ADC_GetCommonPathInternalCh - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Returned value can be a combination of the following values: - * @arg @ref LL_ADC_PATH_INTERNAL_NONE - * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT - * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR - */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance - * @{ - */ - -/** - * @brief Set ADC instance clock source and prescaler. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR2 CKMODE LL_ADC_SetClock - * @param ADCx ADC instance - * @param ClockSource This parameter can be one of the following values: - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2) - * @arg @ref LL_ADC_CLOCK_ASYNC (1) - * - * (1) Asynchronous clock prescaler can be configured using - * function @ref LL_ADC_SetCommonClock().\n - * (2) Caution: This parameter has some clock ratio constraints: - * This configuration must be enabled only if PCLK has a 50% - * duty clock cycle (APB prescaler configured inside the RCC - * must be bypassed and the system clock must by 50% duty - * cycle). - * Refer to reference manual. - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource) -{ - MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); -} - -/** - * @brief Get ADC instance clock source and prescaler. - * @rmtoll CFGR2 CKMODE LL_ADC_GetClock - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 (2) - * @arg @ref LL_ADC_CLOCK_ASYNC (1) - * - * (1) Asynchronous clock prescaler can be retrieved using - * function @ref LL_ADC_GetCommonClock().\n - * (2) Caution: This parameter has some clock ratio constraints: - * This configuration must be enabled only if PCLK has a 50% - * duty clock cycle (APB prescaler configured inside the RCC - * must be bypassed and the system clock must by 50% duty - * cycle). - * Refer to reference manual. - */ -__STATIC_INLINE uint32_t LL_ADC_GetClock(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); -} - -/** - * @brief Set ADC calibration factor in the mode single-ended - * or differential (for devices with differential mode available). - * @note This function is intended to set calibration parameters - * without having to perform a new calibration using - * @ref LL_ADC_StartCalibration(). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be enabled, without calibration on going, without conversion - * on going on group regular. - * @rmtoll CALFACT CALFACT LL_ADC_SetCalibrationFactor - * @param ADCx ADC instance - * @param CalibrationFactor Value between Min_Data=0x00 and Max_Data=0x7F - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t CalibrationFactor) -{ - MODIFY_REG(ADCx->CALFACT, - ADC_CALFACT_CALFACT, - CalibrationFactor); -} - -/** - * @brief Get ADC calibration factor in the mode single-ended - * or differential (for devices with differential mode available). - * @note Calibration factors are set by hardware after performing - * a calibration run using function @ref LL_ADC_StartCalibration(). - * @rmtoll CALFACT CALFACT LL_ADC_GetCalibrationFactor - * @param ADCx ADC instance - * @retval Value between Min_Data=0x00 and Max_Data=0x7F - */ -__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT)); -} - -/** - * @brief Set ADC resolution. - * Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR1 RES LL_ADC_SetResolution - * @param ADCx ADC instance - * @param Resolution This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RES, Resolution); -} - -/** - * @brief Get ADC resolution. - * Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @rmtoll CFGR1 RES LL_ADC_GetResolution - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - */ -__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES)); -} - -/** - * @brief Set ADC conversion data alignment. - * @note Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment - * @param ADCx ADC instance - * @param DataAlignment This parameter can be one of the following values: - * @arg @ref LL_ADC_DATA_ALIGN_RIGHT - * @arg @ref LL_ADC_DATA_ALIGN_LEFT - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment); -} - -/** - * @brief Get ADC conversion data alignment. - * @note Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_DATA_ALIGN_RIGHT - * @arg @ref LL_ADC_DATA_ALIGN_LEFT - */ -__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN)); -} - -/** - * @brief Set ADC low power mode. - * @note Description of ADC low power modes: - * - ADC low power mode "auto wait": Dynamic low power mode, - * ADC conversions occurrences are limited to the minimum necessary - * in order to reduce power consumption. - * New ADC conversion starts only when the previous - * unitary conversion data (for ADC group regular) - * has been retrieved by user software. - * In the meantime, ADC remains idle: does not performs any - * other conversion. - * This mode allows to automatically adapt the ADC conversions - * triggers to the speed of the software that reads the data. - * Moreover, this avoids risk of overrun for low frequency - * applications. - * How to use this low power mode: - * - It is not recommended to use with interruption or DMA - * since these modes have to clear immediately the EOC flag - * (by CPU to free the IRQ pending event or by DMA). - * Auto wait will work but fort a very short time, discarding - * its intended benefit (except specific case of high load of CPU - * or DMA transfers which can justify usage of auto wait). - * - Do use with polling: 1. Start conversion, - * 2. Later on, when conversion data is needed: poll for end of - * conversion to ensure that conversion is completed and - * retrieve ADC conversion data. This will trig another - * ADC conversion start. - * - ADC low power mode "auto power-off" (feature available on - * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): - * the ADC automatically powers-off after a conversion and - * automatically wakes up when a new conversion is triggered - * (with startup time between trigger and start of sampling). - * This feature can be combined with low power mode "auto wait". - * @note With ADC low power mode "auto wait", the ADC conversion data read - * is corresponding to previous ADC conversion start, independently - * of delay during which ADC was idle. - * Therefore, the ADC conversion data may be outdated: does not - * correspond to the current voltage level on the selected - * ADC channel. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode\n - * CFGR1 AUTOFF LL_ADC_SetLowPowerMode - * @param ADCx ADC instance - * @param LowPowerMode This parameter can be one of the following values: - * @arg @ref LL_ADC_LP_MODE_NONE - * @arg @ref LL_ADC_LP_AUTOWAIT - * @arg @ref LL_ADC_LP_AUTOPOWEROFF - * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode) -{ - MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF), LowPowerMode); -} - -/** - * @brief Get ADC low power mode: - * @note Description of ADC low power modes: - * - ADC low power mode "auto wait": Dynamic low power mode, - * ADC conversions occurrences are limited to the minimum necessary - * in order to reduce power consumption. - * New ADC conversion starts only when the previous - * unitary conversion data (for ADC group regular) - * has been retrieved by user software. - * In the meantime, ADC remains idle: does not performs any - * other conversion. - * This mode allows to automatically adapt the ADC conversions - * triggers to the speed of the software that reads the data. - * Moreover, this avoids risk of overrun for low frequency - * applications. - * How to use this low power mode: - * - It is not recommended to use with interruption or DMA - * since these modes have to clear immediately the EOC flag - * (by CPU to free the IRQ pending event or by DMA). - * Auto wait will work but fort a very short time, discarding - * its intended benefit (except specific case of high load of CPU - * or DMA transfers which can justify usage of auto wait). - * - Do use with polling: 1. Start conversion, - * 2. Later on, when conversion data is needed: poll for end of - * conversion to ensure that conversion is completed and - * retrieve ADC conversion data. This will trig another - * ADC conversion start. - * - ADC low power mode "auto power-off" (feature available on - * this device if parameter LL_ADC_LP_AUTOPOWEROFF is available): - * the ADC automatically powers-off after a conversion and - * automatically wakes up when a new conversion is triggered - * (with startup time between trigger and start of sampling). - * This feature can be combined with low power mode "auto wait". - * @note With ADC low power mode "auto wait", the ADC conversion data read - * is corresponding to previous ADC conversion start, independently - * of delay during which ADC was idle. - * Therefore, the ADC conversion data may be outdated: does not - * correspond to the current voltage level on the selected - * ADC channel. - * @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode\n - * CFGR1 AUTOFF LL_ADC_GetLowPowerMode - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_LP_MODE_NONE - * @arg @ref LL_ADC_LP_AUTOWAIT - * @arg @ref LL_ADC_LP_AUTOPOWEROFF - * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF - */ -__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF))); -} - -/** - * @brief Set ADC trigger frequency mode. - * @note ADC trigger frequency mode must be set to low frequency when - * a duration is exceeded before ADC conversion start trigger event - * (between ADC enable and ADC conversion start trigger event - * or between two ADC conversion start trigger event). - * Duration value: Refer to device datasheet, parameter "tIdle". - * @note When ADC trigger frequency mode is set to low frequency, - * some rearm cycles are inserted before performing ADC conversion - * start, inducing a delay of 2 ADC clock cycles. - * @note Usage of ADC trigger frequency mode with ADC low power mode: - * - Low power mode auto wait: Only the first ADC conversion - * start trigger inserts the rearm delay. - * - Low power mode auto power-off: ADC trigger frequency mode - * is discarded. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR2 LFTRIG LL_ADC_SetTriggerFrequencyMode - * @param ADCx ADC instance - * @param TriggerFrequencyMode This parameter can be one of the following values: - * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH - * @arg @ref LL_ADC_TRIGGER_FREQ_LOW - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t TriggerFrequencyMode) -{ - MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_LFTRIG, TriggerFrequencyMode); -} - -/** - * @brief Get ADC trigger frequency mode. - * @rmtoll CFGR2 LFTRIG LL_ADC_GetTriggerFrequencyMode - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH - * @arg @ref LL_ADC_TRIGGER_FREQ_LOW - */ -__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)); -} - -/** - * @brief Set sampling time common to a group of channels. - * @note Unit: ADC clock cycles. - * @note On this STM32 series, sampling time scope is on ADC instance: - * Sampling time common to all channels. - * (on some other STM32 families, sampling time is channel wise) - * @note In case of internal channel (VrefInt, TempSensor, ...) to be - * converted: - * sampling time constraints must be respected (sampling time can be - * adjusted in function of ADC clock frequency and sampling time - * setting). - * Refer to device datasheet for timings values (parameters TS_vrefint, - * TS_temp, ...). - * @note Conversion time is the addition of sampling time and processing time. - * On this STM32 series, ADC processing time is: - * - 12.5 ADC clock cycles at ADC resolution 12 bits - * - 10.5 ADC clock cycles at ADC resolution 10 bits - * - 8.5 ADC clock cycles at ADC resolution 8 bits - * - 6.5 ADC clock cycles at ADC resolution 6 bits - * @note In case of ADC conversion of internal channel (VrefInt, - * temperature sensor, ...), a sampling time minimum value - * is required. - * Refer to device datasheet. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll SMPR SMP1 LL_ADC_SetSamplingTimeCommonChannels\n - * @rmtoll SMPR SMP2 LL_ADC_SetSamplingTimeCommonChannels - * @param ADCx ADC instance - * @param SamplingTimeY This parameter can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 - * @param SamplingTime This parameter can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 - * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY, - uint32_t SamplingTime) -{ - MODIFY_REG(ADCx->SMPR, - ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK), - SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); -} - -/** - * @brief Get sampling time common to a group of channels. - * @note Unit: ADC clock cycles. - * @note On this STM32 series, sampling time scope is on ADC instance: - * Sampling time common to all channels. - * (on some other STM32 families, sampling time is channel wise) - * @note Conversion time is the addition of sampling time and processing time. - * Refer to reference manual for ADC processing time of - * this STM32 series. - * @rmtoll SMPR SMP1 LL_ADC_GetSamplingTimeCommonChannels\n - * @rmtoll SMPR SMP2 LL_ADC_GetSamplingTimeCommonChannels - * @param ADCx ADC instance - * @param SamplingTimeY This parameter can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_1CYCLE_5 - * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_12CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_19CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 - */ -__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY) -{ - return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK))) - >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular - * @{ - */ - -/** - * @brief Set ADC group regular conversion trigger source: - * internal (SW start) or from external peripheral (timer event, - * external interrupt line). - * @note On this STM32 series, setting trigger source to external trigger - * also set trigger polarity to rising edge - * (default setting for compatibility with some ADC on other - * STM32 families having this setting set by HW default value). - * In case of need to modify trigger edge, use - * function @ref LL_ADC_REG_SetTriggerEdge(). - * @note On this STM32 series, ADC trigger frequency mode must be set - * in function of frequency of ADC group regular conversion trigger. - * Refer to description of function - * @ref LL_ADC_SetTriggerFrequencyMode(). - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n - * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource - * @param ADCx ADC instance - * @param TriggerSource This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_SOFTWARE - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 - * (1) ADC external trigger available on STM32C071xx device only. - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource); -} - -/** - * @brief Get ADC group regular conversion trigger source: - * internal (SW start) or from external peripheral (timer event, - * external interrupt line). - * @note To determine whether group regular trigger source is - * internal (SW start) or external, without detail - * of which peripheral is selected as external trigger, - * (equivalent to - * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") - * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n - * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_SOFTWARE - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_TRGO (1) - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 - * (1) ADC external trigger available on STM32C071xx device only. - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx) -{ - __IO uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); - - /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ - /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */ - uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2UL)); - - /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */ - /* to match with triggers literals definition. */ - return ((TriggerSource - & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL) - | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN) - ); -} - -/** - * @brief Get ADC group regular conversion trigger source internal (SW start) - * or external. - * @note In case of group regular trigger source set to external trigger, - * to determine which peripheral is selected as external trigger, - * use function @ref LL_ADC_REG_GetTriggerSource(). - * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart - * @param ADCx ADC instance - * @retval Value "0" if trigger source external trigger - * Value "1" if trigger source SW start. - */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL); -} - -/** - * @brief Set ADC group regular conversion trigger polarity. - * @note Applicable only for trigger source set to external trigger. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge - * @param ADCx ADC instance - * @param ExternalTriggerEdge This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_EXT_RISING - * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING - * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge); -} - -/** - * @brief Get ADC group regular conversion trigger polarity. - * @note Applicable only for trigger source set to external trigger. - * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_EXT_RISING - * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING - * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN)); -} - -/** - * @brief Set ADC group regular sequencer configuration flexibility. - * @note On this STM32 series, ADC group regular sequencer both modes - * "fully configurable" or "not fully configurable" are - * available: - * - sequencer configured to fully configurable: - * sequencer length and each rank - * affectation to a channel are configurable. - * Refer to description of function - * @ref LL_ADC_REG_SetSequencerLength(). - * - sequencer configured to not fully configurable: - * sequencer length and each rank affectation to a channel - * are fixed by channel HW number. - * Refer to description of function - * @ref LL_ADC_REG_SetSequencerChannels(). - * @note On this STM32 series, after modifying sequencer (functions - * @ref LL_ADC_REG_SetSequencerLength() - * @ref LL_ADC_REG_SetSequencerRanks(), ...) - * it is mandatory to wait for the assertion of CCRDY flag - * Otherwise, some actions may be ignored. - * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY - * for more details. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable - * @param ADCx ADC instance - * @param Configurability This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_FIXED - * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint32_t Configurability) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD, Configurability); -} - -/** - * @brief Get ADC group regular sequencer configuration flexibility. - * @note On this STM32 series, ADC group regular sequencer both modes - * "fully configurable" or "not fully configurable" are - * available: - * - sequencer configured to fully configurable: - * sequencer length and each rank - * affectation to a channel are configurable. - * Refer to description of function - * @ref LL_ADC_REG_SetSequencerLength(). - * - sequencer configured to not fully configurable: - * sequencer length and each rank affectation to a channel - * are fixed by channel HW number. - * Refer to description of function - * @ref LL_ADC_REG_SetSequencerChannels(). - * @rmtoll CFGR CHSELRMOD LL_ADC_REG_SetSequencerConfigurable - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_FIXED - * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD)); -} - -/** - * @brief Set ADC group regular sequencer length and scan direction. - * @note Description of ADC group regular sequencer features: - * - For devices with sequencer fully configurable - * (function "LL_ADC_REG_SetSequencerRanks()" available): - * sequencer length and each rank affectation to a channel - * are configurable. - * This function performs configuration of: - * - Sequence length: Number of ranks in the scan sequence. - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from rank 1 to rank n). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerRanks()". - * - For devices with sequencer not fully configurable - * (function "LL_ADC_REG_SetSequencerChannels()" available): - * sequencer length and each rank affectation to a channel - * are defined by channel number. - * This function performs configuration of: - * - Sequence length: Number of ranks in the scan sequence is - * defined by number of channels set in the sequence, - * rank of each channel is fixed by channel HW number. - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from lowest channel number to - * highest channel number). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerChannels()". - * To set scan direction differently, refer to function - * @ref LL_ADC_REG_SetSequencerScanDirection(). - * @note On this STM32 series, ADC group regular sequencer both modes - * "fully configurable" or "not fully configurable" - * are available, they can be chosen using - * function @ref LL_ADC_REG_SetSequencerConfigurable(). - * @note On this STM32 series, after modifying sequencer (functions - * @ref LL_ADC_REG_SetSequencerLength() - * @ref LL_ADC_REG_SetSequencerRanks(), ...) - * it is mandatory to wait for the assertion of CCRDY flag - * using @ref LL_ADC_IsActiveFlag_CCRDY(). - * Otherwise, some actions may be ignored. - * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY - * for more details. - * @note Sequencer disabled is equivalent to sequencer of 1 rank: - * ADC conversion on only 1 channel. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerLength\n - * CHSELR SQ2 LL_ADC_REG_SetSequencerLength\n - * CHSELR SQ3 LL_ADC_REG_SetSequencerLength\n - * CHSELR SQ4 LL_ADC_REG_SetSequencerLength\n - * CHSELR SQ5 LL_ADC_REG_SetSequencerLength\n - * CHSELR SQ6 LL_ADC_REG_SetSequencerLength\n - * CHSELR SQ7 LL_ADC_REG_SetSequencerLength\n - * CHSELR SQ8 LL_ADC_REG_SetSequencerLength - * @param ADCx ADC instance - * @param SequencerNbRanks This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t SequencerNbRanks) -{ - SET_BIT(ADCx->CHSELR, SequencerNbRanks); -} - -/** - * @brief Get ADC group regular sequencer length and scan direction. - * @note Description of ADC group regular sequencer features: - * - For devices with sequencer fully configurable - * (function "LL_ADC_REG_SetSequencerRanks()" available): - * sequencer length and each rank affectation to a channel - * are configurable. - * This function retrieves: - * - Sequence length: Number of ranks in the scan sequence. - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from rank 1 to rank n). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerRanks()". - * - For devices with sequencer not fully configurable - * (function "LL_ADC_REG_SetSequencerChannels()" available): - * sequencer length and each rank affectation to a channel - * are defined by channel number. - * This function retrieves: - * - Sequence length: Number of ranks in the scan sequence is - * defined by number of channels set in the sequence, - * rank of each channel is fixed by channel HW number. - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * - Sequence direction: Unless specified in parameters, sequencer - * scan direction is forward (from lowest channel number to - * highest channel number). - * Sequencer ranks are selected using - * function "LL_ADC_REG_SetSequencerChannels()". - * To set scan direction differently, refer to function - * @ref LL_ADC_REG_SetSequencerScanDirection(). - * @note On this STM32 series, ADC group regular sequencer both modes - * "fully configurable" or "not fully configurable" - * are available, they can be chosen using - * function @ref LL_ADC_REG_SetSequencerConfigurable(). - * @note Sequencer disabled is equivalent to sequencer of 1 rank: - * ADC conversion on only 1 channel. - * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerLength\n - * CHSELR SQ2 LL_ADC_REG_GetSequencerLength\n - * CHSELR SQ3 LL_ADC_REG_GetSequencerLength\n - * CHSELR SQ4 LL_ADC_REG_GetSequencerLength\n - * CHSELR SQ5 LL_ADC_REG_GetSequencerLength\n - * CHSELR SQ6 LL_ADC_REG_GetSequencerLength\n - * CHSELR SQ7 LL_ADC_REG_GetSequencerLength\n - * CHSELR SQ8 LL_ADC_REG_GetSequencerLength - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_SCAN_DISABLE - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS - * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) -{ - __IO uint32_t ChannelsRanks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL); - uint32_t SequencerLength = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS; - uint32_t RankIndex; - - /* Parse register for end of sequence identifier */ - for (RankIndex = 0UL; RankIndex < (32U - 4U); RankIndex += 4U) - { - if ((ChannelsRanks & (ADC_CHSELR_SQ2 << RankIndex)) == (ADC_CHSELR_SQ2 << RankIndex)) - { - SequencerLength = (ADC_CHSELR_SQ2 << RankIndex); - break; - } - } - - return SequencerLength; -} - -/** - * @brief Set ADC group regular sequencer scan direction. - * @note On this STM32 series, parameter relevant only is sequencer is set - * to mode not fully configurable, - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). - * @note On some other STM32 series, this setting is not available and - * the default scan direction is forward. - * @note On this STM32 series, after modifying sequencer (functions - * @ref LL_ADC_REG_SetSequencerLength() - * @ref LL_ADC_REG_SetSequencerRanks(), ...) - * it is mandatory to wait for the assertion of CCRDY flag - * using @ref LL_ADC_IsActiveFlag_CCRDY(). - * Otherwise, some actions may be ignored. - * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY - * for more details. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection - * @param ADCx ADC instance - * @param ScanDirection This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD - * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection); -} - -/** - * @brief Get ADC group regular sequencer scan direction. - * @note On this STM32 series, parameter relevant only is sequencer is set - * to mode not fully configurable, - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). - * @note On some other STM32 families, this setting is not available and - * the default scan direction is forward. - * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD - * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR)); -} - -/** - * @brief Set ADC group regular sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @note It is not possible to enable both ADC group regular - * continuous mode and sequencer discontinuous mode. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n - * @param ADCx ADC instance - * @param SeqDiscont This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont); -} - -/** - * @brief Get ADC group regular sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN)); -} - -/** - * @brief Set ADC group regular sequence: channel on the selected - * scan sequence rank. - * @note This function performs configuration of: - * - Channels ordering into each rank of scan sequence: - * whatever channel can be placed into whatever rank. - * @note On this STM32 series, ADC group regular sequencer is - * fully configurable: sequencer length and each rank - * affectation to a channel are configurable. - * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note On this STM32 series, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this STM32 series, after modifying sequencer (functions - * @ref LL_ADC_REG_SetSequencerLength() - * @ref LL_ADC_REG_SetSequencerRanks(), ...) - * it is mandatory to wait for the assertion of CCRDY flag - * using @ref LL_ADC_IsActiveFlag_CCRDY(). - * Otherwise, some actions may be ignored. - * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY - * for more details. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CHSELR SQ1 LL_ADC_REG_SetSequencerRanks\n - * CHSELR SQ2 LL_ADC_REG_SetSequencerRanks\n - * CHSELR SQ3 LL_ADC_REG_SetSequencerRanks\n - * CHSELR SQ4 LL_ADC_REG_SetSequencerRanks\n - * CHSELR SQ5 LL_ADC_REG_SetSequencerRanks\n - * CHSELR SQ6 LL_ADC_REG_SetSequencerRanks\n - * CHSELR SQ7 LL_ADC_REG_SetSequencerRanks\n - * CHSELR SQ8 LL_ADC_REG_SetSequencerRanks - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_RANK_1 - * @arg @ref LL_ADC_REG_RANK_2 - * @arg @ref LL_ADC_REG_RANK_3 - * @arg @ref LL_ADC_REG_RANK_4 - * @arg @ref LL_ADC_REG_RANK_5 - * @arg @ref LL_ADC_REG_RANK_6 - * @arg @ref LL_ADC_REG_RANK_7 - * @arg @ref LL_ADC_REG_RANK_8 - * @param Channel This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank, uint32_t Channel) -{ - /* Set bits with content of parameter "Channel" with bits position */ - /* in register depending on parameter "Rank". */ - /* Parameters "Rank" and "Channel" are used with masks because containing */ - /* other bits reserved for other purpose. */ - MODIFY_REG(ADCx->CHSELR, - ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), - ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) - << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); -} - -/** - * @brief Get ADC group regular sequence: channel on the selected - * scan sequence rank. - * @note On this STM32 series, ADC group regular sequencer is - * fully configurable: sequencer length and each rank - * affectation to a channel are configurable. - * Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note Usage of the returned channel number: - * - To reinject this channel into another function LL_ADC_xxx: - * the returned channel number is only partly formatted on definition - * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared - * with parts of literals LL_ADC_CHANNEL_x or using - * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Then the selected literal LL_ADC_CHANNEL_x can be used - * as parameter for another function. - * - To get the channel number in decimal format: - * process the returned value with the helper macro - * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * @rmtoll CHSELR SQ1 LL_ADC_REG_GetSequencerRanks\n - * CHSELR SQ2 LL_ADC_REG_GetSequencerRanks\n - * CHSELR SQ3 LL_ADC_REG_GetSequencerRanks\n - * CHSELR SQ4 LL_ADC_REG_GetSequencerRanks\n - * CHSELR SQ5 LL_ADC_REG_GetSequencerRanks\n - * CHSELR SQ6 LL_ADC_REG_GetSequencerRanks\n - * CHSELR SQ7 LL_ADC_REG_GetSequencerRanks\n - * CHSELR SQ8 LL_ADC_REG_GetSequencerRanks - * @param ADCx ADC instance - * @param Rank This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_RANK_1 - * @arg @ref LL_ADC_REG_RANK_2 - * @arg @ref LL_ADC_REG_RANK_3 - * @arg @ref LL_ADC_REG_RANK_4 - * @arg @ref LL_ADC_REG_RANK_5 - * @arg @ref LL_ADC_REG_RANK_6 - * @arg @ref LL_ADC_REG_RANK_7 - * @arg @ref LL_ADC_REG_RANK_8 - * @retval Returned value can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) -{ - return (uint32_t)((READ_BIT(ADCx->CHSELR, - ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) - >> (Rank & ADC_REG_RANK_ID_SQRX_MASK) - ) << (ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) - ); -} - -/** - * @brief Set ADC group regular sequence: channel on rank corresponding to - * channel number. - * @note This function performs: - * - Channels ordering into each rank of scan sequence: - * rank of each channel is fixed by channel HW number - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * - Set channels selected by overwriting the current sequencer - * configuration. - * @note On this STM32 series, ADC group regular sequencer both modes - * "fully configurable" or "not fully configurable" - * are available, they can be chosen using - * function @ref LL_ADC_REG_SetSequencerConfigurable(). - * This function can be used with setting "not fully configurable". - * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() - * and @ref LL_ADC_REG_SetSequencerLength(). - * @note On this STM32 series, after modifying sequencer (functions - * @ref LL_ADC_REG_SetSequencerLength() - * @ref LL_ADC_REG_SetSequencerRanks(), ...) - * it is mandatory to wait for the assertion of CCRDY flag - * using @ref LL_ADC_IsActiveFlag_CCRDY(). - * Otherwise, some actions may be ignored. - * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY - * for more details. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note On this STM32 series, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @note One or several values can be selected. - * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChannels - * @param ADCx ADC instance - * @param Channel This parameter can be a combination of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel) -{ - /* Parameter "Channel" is used with masks because containing */ - /* other bits reserved for other purpose. */ - WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); -} - -/** - * @brief Add channel to ADC group regular sequence: channel on rank corresponding to - * channel number. - * @note This function performs: - * - Channels ordering into each rank of scan sequence: - * rank of each channel is fixed by channel HW number - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * - Set channels selected by adding them to the current sequencer - * configuration. - * @note On this STM32 series, ADC group regular sequencer both modes - * "fully configurable" or "not fully configurable" - * are available, they can be chosen using - * function @ref LL_ADC_REG_SetSequencerConfigurable(). - * This function can be used with setting "not fully configurable". - * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() - * and @ref LL_ADC_REG_SetSequencerLength(). - * @note On this STM32 series, after modifying sequencer (functions - * @ref LL_ADC_REG_SetSequencerLength() - * @ref LL_ADC_REG_SetSequencerRanks(), ...) - * it is mandatory to wait for the assertion of CCRDY flag - * using @ref LL_ADC_IsActiveFlag_CCRDY(). - * Otherwise, some actions may be ignored. - * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY - * for more details. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note On this STM32 series, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @note One or several values can be selected. - * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChAdd - * @param ADCx ADC instance - * @param Channel This parameter can be a combination of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel) -{ - /* Parameter "Channel" is used with masks because containing */ - /* other bits reserved for other purpose. */ - SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); -} - -/** - * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to - * channel number. - * @note This function performs: - * - Channels ordering into each rank of scan sequence: - * rank of each channel is fixed by channel HW number - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * - Set channels selected by removing them to the current sequencer - * configuration. - * @note On this STM32 series, ADC group regular sequencer both modes - * "fully configurable" or "not fully configurable" - * are available, they can be chosen using - * function @ref LL_ADC_REG_SetSequencerConfigurable(). - * This function can be used with setting "not fully configurable". - * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() - * and @ref LL_ADC_REG_SetSequencerLength(). - * @note On this STM32 series, after modifying sequencer (functions - * @ref LL_ADC_REG_SetSequencerLength() - * @ref LL_ADC_REG_SetSequencerRanks(), ...) - * it is mandatory to wait for the assertion of CCRDY flag - * using @ref LL_ADC_IsActiveFlag_CCRDY(). - * Otherwise, some actions may be ignored. - * Refer to description of @ref LL_ADC_IsActiveFlag_CCRDY - * for more details. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note On this STM32 series, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @note One or several values can be selected. - * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL10 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL13 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL14 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL15 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL16 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL17 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL18 LL_ADC_REG_SetSequencerChRem - * @param ADCx ADC instance - * @param Channel This parameter can be a combination of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel) -{ - /* Parameter "Channel" is used with masks because containing */ - /* other bits reserved for other purpose. */ - CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); -} - -/** - * @brief Get ADC group regular sequence: channel on rank corresponding to - * channel number. - * @note This function performs: - * - Channels order reading into each rank of scan sequence: - * rank of each channel is fixed by channel HW number - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * @note On this STM32 series, ADC group regular sequencer both modes - * "fully configurable" or "not fully configurable" - * are available, they can be chosen using - * function @ref LL_ADC_REG_SetSequencerConfigurable(). - * This function can be used with setting "not fully configurable". - * Refer to description of functions @ref LL_ADC_REG_SetSequencerConfigurable() - * and @ref LL_ADC_REG_SetSequencerLength(). - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note On this STM32 series, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @note One or several values can be retrieved. - * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL10 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL13 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL14 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL15 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL16 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL17 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL18 LL_ADC_REG_GetSequencerChannels - * @param ADCx ADC instance - * @retval Returned value can be a combination of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx) -{ - uint32_t ChannelsBitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); - - return ((((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL10) >> ADC_CHSELR_CHSEL10_BITOFFSET_POS) * LL_ADC_CHANNEL_10) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL13) >> ADC_CHSELR_CHSEL13_BITOFFSET_POS) * LL_ADC_CHANNEL_13) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL14) >> ADC_CHSELR_CHSEL14_BITOFFSET_POS) * LL_ADC_CHANNEL_14) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL15) >> ADC_CHSELR_CHSEL15_BITOFFSET_POS) * LL_ADC_CHANNEL_15) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL16) >> ADC_CHSELR_CHSEL16_BITOFFSET_POS) * LL_ADC_CHANNEL_16) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL17) >> ADC_CHSELR_CHSEL17_BITOFFSET_POS) * LL_ADC_CHANNEL_17) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL18) >> ADC_CHSELR_CHSEL18_BITOFFSET_POS) * LL_ADC_CHANNEL_18) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL19) >> ADC_CHSELR_CHSEL19_BITOFFSET_POS) * LL_ADC_CHANNEL_19) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL20) >> ADC_CHSELR_CHSEL20_BITOFFSET_POS) * LL_ADC_CHANNEL_20) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL21) >> ADC_CHSELR_CHSEL21_BITOFFSET_POS) * LL_ADC_CHANNEL_21) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL22) >> ADC_CHSELR_CHSEL22_BITOFFSET_POS) * LL_ADC_CHANNEL_22) - ); -} - -/** - * @brief Set ADC continuous conversion mode on ADC group regular. - * @note Description of ADC continuous conversion mode: - * - single mode: one conversion per trigger - * - continuous mode: after the first trigger, following - * conversions launched successively automatically. - * @note It is not possible to enable both ADC group regular - * continuous mode and sequencer discontinuous mode. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode - * @param ADCx ADC instance - * @param Continuous This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_CONV_SINGLE - * @arg @ref LL_ADC_REG_CONV_CONTINUOUS - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous); -} - -/** - * @brief Get ADC continuous conversion mode on ADC group regular. - * @note Description of ADC continuous conversion mode: - * - single mode: one conversion per trigger - * - continuous mode: after the first trigger, following - * conversions launched successively automatically. - * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_CONV_SINGLE - * @arg @ref LL_ADC_REG_CONV_CONTINUOUS - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT)); -} - -/** - * @brief Set ADC group regular conversion data transfer: no transfer or - * transfer by DMA, and DMA requests mode. - * @note If transfer by DMA selected, specifies the DMA requests - * mode: - * - Limited mode (One shot mode): DMA transfer requests are stopped - * when number of DMA data transfers (number of - * ADC conversions) is reached. - * This ADC mode is intended to be used with DMA mode non-circular. - * - Unlimited mode: DMA transfer requests are unlimited, - * whatever number of DMA data transfers (number of - * ADC conversions). - * This ADC mode is intended to be used with DMA mode circular. - * @note If ADC DMA requests mode is set to unlimited and DMA is set to - * mode non-circular: - * when DMA transfers size will be reached, DMA will stop transfers of - * ADC conversions data ADC will raise an overrun error - * (overrun flag and interruption if enabled). - * @note To configure DMA source address (peripheral address), - * use function @ref LL_ADC_DMA_GetRegAddr(). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n - * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer - * @param ADCx ADC instance - * @param DMATransfer This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE - * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED - * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer); -} - -/** - * @brief Get ADC group regular conversion data transfer: no transfer or - * transfer by DMA, and DMA requests mode. - * @note If transfer by DMA selected, specifies the DMA requests - * mode: - * - Limited mode (One shot mode): DMA transfer requests are stopped - * when number of DMA data transfers (number of - * ADC conversions) is reached. - * This ADC mode is intended to be used with DMA mode non-circular. - * - Unlimited mode: DMA transfer requests are unlimited, - * whatever number of DMA data transfers (number of - * ADC conversions). - * This ADC mode is intended to be used with DMA mode circular. - * @note If ADC DMA requests mode is set to unlimited and DMA is set to - * mode non-circular: - * when DMA transfers size will be reached, DMA will stop transfers of - * ADC conversions data ADC will raise an overrun error - * (overrun flag and interruption if enabled). - * @note To configure DMA source address (peripheral address), - * use function @ref LL_ADC_DMA_GetRegAddr(). - * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n - * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE - * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED - * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG)); -} - -/** - * @brief Set ADC group regular behavior in case of overrun: - * data preserved or overwritten. - * @note Compatibility with devices without feature overrun: - * other devices without this feature have a behavior - * equivalent to data overwritten. - * The default setting of overrun is data preserved. - * Therefore, for compatibility with all devices, parameter - * overrun should be set to data overwritten. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun - * @param ADCx ADC instance - * @param Overrun This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED - * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun); -} - -/** - * @brief Get ADC group regular behavior in case of overrun: - * data preserved or overwritten. - * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED - * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_Channels Configuration of ADC hierarchical scope: channels - * @{ - */ - -/** - * @brief Set sampling time of the selected ADC channel - * Unit: ADC clock cycles. - * @note On this device, sampling time is on channel scope: independently - * of channel mapped on ADC group regular or injected. - * @note In case of internal channel (VrefInt, TempSensor, ...) to be - * converted: - * sampling time constraints must be respected (sampling time can be - * adjusted in function of ADC clock frequency and sampling time - * setting). - * Refer to device datasheet for timings values (parameters TS_vrefint, - * TS_temp, ...). - * @note Conversion time is the addition of sampling time and processing time. - * Refer to reference manual for ADC processing time of - * this STM32 series. - * @note In case of ADC conversion of internal channel (VrefInt, - * temperature sensor, ...), a sampling time minimum value - * is required. - * Refer to device datasheet. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll SMPR SMPSEL0 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL1 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL2 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL3 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL4 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL5 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL6 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL7 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL8 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL9 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL10 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL11 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL12 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL13 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL14 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL15 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL16 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL17 LL_ADC_SetChannelSamplingTime\n - * SMPR SMPSEL18 LL_ADC_SetChannelSamplingTime - * @param ADCx ADC instance - * @param Channel This parameter can be a combination of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - * @param SamplingTimeY This parameter can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel, uint32_t SamplingTimeY) -{ - /* Parameter "Channel" is used with masks because containing */ - /* other bits reserved for other purpose. */ - MODIFY_REG(ADCx->SMPR, - (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS), - (Channel << ADC_SMPR_SMPSEL0_BITOFFSET_POS) & (SamplingTimeY & ADC_SAMPLING_TIME_CH_MASK) - ); -} - -/** - * @brief Get sampling time of the selected ADC channel - * Unit: ADC clock cycles. - * @note On this device, sampling time is on channel scope: independently - * of channel mapped on ADC group regular or injected. - * @note Conversion time is the addition of sampling time and processing time. - * Refer to reference manual for ADC processing time of - * this STM32 series. - * @rmtoll SMPR SMPSEL0 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL1 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL2 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL3 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL4 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL5 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL6 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL7 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL8 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL9 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL10 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL11 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL12 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL13 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL14 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL15 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL16 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL17 LL_ADC_GetChannelSamplingTime\n - * SMPR SMPSEL18 LL_ADC_GetChannelSamplingTime - * @param ADCx ADC instance - * @param Channel This parameter can be one of the following values: - * @arg @ref ADC_CHANNEL_0 - * @arg @ref ADC_CHANNEL_1 - * @arg @ref ADC_CHANNEL_2 - * @arg @ref ADC_CHANNEL_3 - * @arg @ref ADC_CHANNEL_4 - * @arg @ref ADC_CHANNEL_5 - * @arg @ref ADC_CHANNEL_6 - * @arg @ref ADC_CHANNEL_7 - * @arg @ref ADC_CHANNEL_8 (1) - * @arg @ref ADC_CHANNEL_9 (1) - * @arg @ref ADC_CHANNEL_10 - * @arg @ref ADC_CHANNEL_11 - * @arg @ref ADC_CHANNEL_12 - * @arg @ref ADC_CHANNEL_13 - * @arg @ref ADC_CHANNEL_14 - * @arg @ref ADC_CHANNEL_15 (1) - * @arg @ref ADC_CHANNEL_16 (1) - * @arg @ref ADC_CHANNEL_17 (3) - * @arg @ref ADC_CHANNEL_18 (3) - * @arg @ref ADC_CHANNEL_19 (3) - * @arg @ref ADC_CHANNEL_20 (3) - * @arg @ref ADC_CHANNEL_21 (3) - * @arg @ref ADC_CHANNEL_22 (3) - * @arg @ref ADC_CHANNEL_VREFINT (2) - * @arg @ref ADC_CHANNEL_TEMPSENSOR (2) - * @arg @ref ADC_CHANNEL_VDDA (2) - * @arg @ref ADC_CHANNEL_VSSA (2) - * - * (1) On STM32C0, parameter can be set in ADC group sequencer - * only if sequencer is set in mode "not fully configurable", - * refer to function @ref LL_ADC_REG_SetSequencerConfigurable().\n - * (2) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * (3) ADC channels available on STM32C031xx device only. - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 - * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 - */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel) -{ - __IO uint32_t smpr = READ_REG(ADCx->SMPR); - - /* Retrieve sampling time bit corresponding to the selected channel */ - /* and shift it to position 0. */ - uint32_t smp_channel_posbit0 = ((smpr & ADC_SAMPLING_TIME_CH_MASK) - >> ((((Channel & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) - + ADC_SMPR_SMPSEL0_BITOFFSET_POS) - & 0x1FUL)); - - /* Select sampling time bitfield depending on sampling time bit value 0 or 1. */ - return ((~(smp_channel_posbit0) * LL_ADC_SAMPLINGTIME_COMMON_1) - | (smp_channel_posbit0 * LL_ADC_SAMPLINGTIME_COMMON_2)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog - * @{ - */ - -/** - * @brief Set ADC analog watchdog monitored channels: - * a single channel or all channels, - * on ADC group regular. - * @note Once monitored channels are selected, analog watchdog - * is enabled. - * @note In case of need to define a single channel to monitor - * with analog watchdog from sequencer channel definition, - * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). - * @note On this STM32 series, there is only 1 kind of analog watchdog - * instance: - * - AWD standard (instance AWD1): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC group regular. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR1 AWD1CH LL_ADC_SetAnalogWDMonitChannels\n - * CFGR1 AWD1SGL LL_ADC_SetAnalogWDMonitChannels\n - * CFGR1 AWD1EN LL_ADC_SetAnalogWDMonitChannels\n - * AWD2CR AWD2CH LL_ADC_SetAnalogWDMonitChannels\n - * AWD3CR AWD3CH LL_ADC_SetAnalogWDMonitChannels - * @param ADCx ADC instance - * @param AWDy This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD1 - * @arg @ref LL_ADC_AWD2 - * @arg @ref LL_ADC_AWD3 - * @param AWDChannelGroup This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_DISABLE - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1) - * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (1) - * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (1) - * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (1) - * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1) - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG - * @arg @ref LL_ADC_AWD_CH_VDDA_REG - * @arg @ref LL_ADC_AWD_CH_VSSA_REG - * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx. - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDChannelGroup) -{ - /* Set bits with content of parameter "AWDChannelGroup" with bits position */ - /* in register and register position depending on parameter "AWDy". */ - /* Parameters "AWDChannelGroup" and "AWDy" are used with masks because */ - /* containing other bits reserved for other purpose. */ - register __IO uint32_t *preg; - - if (AWDy == LL_ADC_AWD1) - { - preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, 0UL); - } - else - { - preg = __ADC_PTR_REG_OFFSET(ADCx->AWD2CR, - ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK)) >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)); - } - - MODIFY_REG(*preg, - (AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK), - AWDChannelGroup & AWDy); -} - -/** - * @brief Get ADC analog watchdog monitored channel. - * @note Usage of the returned channel number: - * - To reinject this channel into another function LL_ADC_xxx: - * the returned channel number is only partly formatted on definition - * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared - * with parts of literals LL_ADC_CHANNEL_x or using - * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Then the selected literal LL_ADC_CHANNEL_x can be used - * as parameter for another function. - * - To get the channel number in decimal format: - * process the returned value with the helper macro - * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Applicable only when the analog watchdog is set to monitor - * one channel. - * @note On this STM32 series, there is only 1 kind of analog watchdog - * instance: - * - AWD standard (instance AWD1): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC group regular. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * - AWD flexible (instances AWD2, AWD3): - * - channels monitored: flexible on channels monitored, selection is - * channel wise, from from 1 to all channels. - * Specificity of this analog watchdog: Multiple channels can - * be selected. For example: - * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) - * - groups monitored: not selection possible (monitoring on both - * groups regular and injected). - * Channels selected are monitored on groups regular and injected: - * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters - * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR1 AWD1CH LL_ADC_GetAnalogWDMonitChannels\n - * CFGR1 AWD1SGL LL_ADC_GetAnalogWDMonitChannels\n - * CFGR1 AWD1EN LL_ADC_GetAnalogWDMonitChannels\n - * AWD2CR AWD2CH LL_ADC_GetAnalogWDMonitChannels\n - * AWD3CR AWD3CH LL_ADC_GetAnalogWDMonitChannels - * @param ADCx ADC instance - * @param AWDy This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD1 - * @arg @ref LL_ADC_AWD2 (1) - * @arg @ref LL_ADC_AWD3 (1) - * - * (1) On this AWD number, monitored channel can be retrieved - * if only 1 channel is programmed (or none or all channels). - * This function cannot retrieve monitored channel if - * multiple channels are programmed simultaneously - * by bitfield. - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_AWD_DISABLE - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG - * @arg @ref LL_ADC_AWD_CHANNEL_10_REG - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG - * @arg @ref LL_ADC_AWD_CHANNEL_13_REG - * @arg @ref LL_ADC_AWD_CHANNEL_14_REG - * @arg @ref LL_ADC_AWD_CHANNEL_15_REG - * @arg @ref LL_ADC_AWD_CHANNEL_16_REG - * @arg @ref LL_ADC_AWD_CHANNEL_17_REG - * @arg @ref LL_ADC_AWD_CHANNEL_18_REG (1) - * @arg @ref LL_ADC_AWD_CHANNEL_19_REG (1) - * @arg @ref LL_ADC_AWD_CHANNEL_20_REG (1) - * @arg @ref LL_ADC_AWD_CHANNEL_21_REG (1) - * @arg @ref LL_ADC_AWD_CHANNEL_22_REG (1) - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG - * @arg @ref LL_ADC_AWD_CH_VDDA_REG - * @arg @ref LL_ADC_AWD_CH_VSSA_REG - * (1) On STM32C0, parameter not available on all devices: only on STM32C031xx. - */__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) -{ - register __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, - ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) - * ADC_AWD_CR12_REGOFFSETGAP_VAL)); - - register uint32_t AnalogWDMonitChannels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); - - /* If "AnalogWDMonitChannels" == 0, then the selected AWD is disabled */ - /* (parameter value LL_ADC_AWD_DISABLE). */ - /* Else, the selected AWD is enabled and is monitoring a group of channels */ - /* or a single channel. */ - if (AnalogWDMonitChannels != 0UL) - { - if (AWDy == LL_ADC_AWD1) - { - if ((AnalogWDMonitChannels & ADC_CFGR1_AWD1SGL) == 0UL) - { - /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = ((AnalogWDMonitChannels - | (ADC_AWD_CR23_CHANNEL_MASK) - ) - & (~(ADC_CFGR1_AWD1CH)) - ); - } - else - { - /* AWD monitoring a single channel */ - AnalogWDMonitChannels = (AnalogWDMonitChannels - | (ADC_AWD2CR_AWD2CH_0 << (AnalogWDMonitChannels >> ADC_CFGR1_AWD1CH_Pos)) - ); - } - } - else - { - if ((AnalogWDMonitChannels & ADC_AWD_CR23_CHANNEL_MASK) == ADC_AWD_CR23_CHANNEL_MASK) - { - /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = (ADC_AWD_CR23_CHANNEL_MASK - | (ADC_CFGR1_AWD1EN) - ); - } - else - { - /* AWD monitoring a single channel */ - /* AWD monitoring a group of channels */ - AnalogWDMonitChannels = (AnalogWDMonitChannels - | (ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) - | (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDMonitChannels) << ADC_CFGR1_AWD1CH_Pos) - ); - } - } - } - - return AnalogWDMonitChannels; -} -/** - * @brief Set ADC analog watchdog thresholds value of both thresholds - * high and low. - * @note If value of only one threshold high or low must be set, - * use function @ref LL_ADC_SetAnalogWDThresholds(). - * @note In case of ADC resolution different of 12 bits, - * analog watchdog thresholds data require a specific shift. - * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). - * @note On this STM32 series, there is only 2 kind of analog watchdog - * instance: - * - AWD standard (instance AWD1): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC group regular. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * - AWD flexible (instances AWD2, AWD3): - * - channels monitored: flexible on channels monitored, selection is - * channel wise, from from 1 to all channels. - * Specificity of this analog watchdog: Multiple channels can - * be selected. For example: - * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) - * - groups monitored: not selection possible (monitoring on both - * groups regular and injected). - * Channels selected are monitored on groups regular and injected: - * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters - * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are - * impacted: the comparison of analog watchdog thresholds is done on - * oversampling final computation (after ratio and shift application): - * ADC data register bitfield [15:4] (12 most significant bits). - * Examples: - * - Oversampling ratio and shift selected to have ADC conversion data - * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): - * ADC analog watchdog thresholds must be divided by 16. - * - Oversampling ratio and shift selected to have ADC conversion data - * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): - * ADC analog watchdog thresholds must be divided by 4. - * - Oversampling ratio and shift selected to have ADC conversion data - * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): - * ADC analog watchdog thresholds match directly to ADC data register. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll AWD1TR HT1 LL_ADC_ConfigAnalogWDThresholds\n - * AWD2TR HT2 LL_ADC_ConfigAnalogWDThresholds\n - * AWD3TR HT3 LL_ADC_ConfigAnalogWDThresholds\n - * AWD1TR LT1 LL_ADC_ConfigAnalogWDThresholds\n - * AWD2TR LT2 LL_ADC_ConfigAnalogWDThresholds\n - * AWD3TR LT3 LL_ADC_ConfigAnalogWDThresholds - * @param ADCx ADC instance - * @param AWDy This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD1 - * @arg @ref LL_ADC_AWD2 - * @arg @ref LL_ADC_AWD3 - * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF - * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval None - */ -__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdHighValue, - uint32_t AWDThresholdLowValue) -{ - /* Set bits with content of parameter "AWDThresholdxxxValue" with bits */ - /* position in register and register position depending on parameter */ - /* "AWDy". */ - /* Parameters "AWDy" and "AWDThresholdxxxValue" are used with masks because */ - /* containing other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, - (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) - >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) - + ((ADC_AWD_CR3_REGOFFSET & AWDy) - >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)) - ); - - MODIFY_REG(*preg, - ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, - (AWDThresholdHighValue << ADC_TR1_HT1_BITOFFSET_POS) | AWDThresholdLowValue); -} -/** - * @brief Set ADC analog watchdog threshold value of threshold - * high or low. - * @note If values of both thresholds high or low must be set, - * use function @ref LL_ADC_ConfigAnalogWDThresholds(). - * @note In case of ADC resolution different of 12 bits, - * analog watchdog thresholds data require a specific shift. - * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). - * @note On this STM32 series, there is only 2 kinds of analog watchdog - * instance: - * - AWD standard (instance AWD1): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC group regular. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * - AWD flexible (instances AWD2, AWD3): - * - channels monitored: flexible on channels monitored, selection is - * channel wise, from from 1 to all channels. - * Specificity of this analog watchdog: Multiple channels can - * be selected. For example: - * (LL_ADC_AWD_CHANNEL4_REG_INJ | LL_ADC_AWD_CHANNEL5_REG_INJ | ...) - * - groups monitored: not selection possible (monitoring on both - * groups regular and injected). - * Channels selected are monitored on groups regular and injected: - * LL_ADC_AWD_CHANNELxx_REG_INJ (do not use parameters - * LL_ADC_AWD_CHANNELxx_REG and LL_ADC_AWD_CHANNELxx_INJ) - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * @note If ADC oversampling is enabled, ADC analog watchdog thresholds are - * impacted: the comparison of analog watchdog thresholds is done on - * oversampling final computation (after ratio and shift application): - * ADC data register bitfield [15:4] (12 most significant bits). - * Examples: - * - Oversampling ratio and shift selected to have ADC conversion data - * on 12 bits (ratio 16 and shift 4, or ratio 32 and shift 5, ...): - * ADC analog watchdog thresholds must be divided by 16. - * - Oversampling ratio and shift selected to have ADC conversion data - * on 14 bits (ratio 16 and shift 2, or ratio 32 and shift 3, ...): - * ADC analog watchdog thresholds must be divided by 4. - * - Oversampling ratio and shift selected to have ADC conversion data - * on 16 bits (ratio 16 and shift none, or ratio 32 and shift 1, ...): - * ADC analog watchdog thresholds match directly to ADC data register. - * @note On this STM32 series, setting of this feature is not conditioned to - * ADC state: - * ADC can be disabled, enabled with or without conversion on going - * on ADC group regular. - * @rmtoll AWD1TR HT1 LL_ADC_SetAnalogWDThresholds\n - * AWD2TR HT2 LL_ADC_SetAnalogWDThresholds\n - * AWD3TR HT3 LL_ADC_SetAnalogWDThresholds\n - * AWD1TR LT1 LL_ADC_SetAnalogWDThresholds\n - * AWD2TR LT2 LL_ADC_SetAnalogWDThresholds\n - * AWD3TR LT3 LL_ADC_SetAnalogWDThresholds - * @param ADCx ADC instance - * @param AWDy This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD1 - * @arg @ref LL_ADC_AWD2 - * @arg @ref LL_ADC_AWD3 - * @param AWDThresholdsHighLow This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH - * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow, - uint32_t AWDThresholdValue) -{ - /* Set bits with content of parameter "AWDThresholdValue" with bits */ - /* position in register and register position depending on parameters */ - /* "AWDThresholdsHighLow" and "AWDy". */ - /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ - /* containing other bits reserved for other purpose. */ - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, - (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) - >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) - + ((ADC_AWD_CR3_REGOFFSET & AWDy) - >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); - - MODIFY_REG(*preg, - AWDThresholdsHighLow, - AWDThresholdValue << ((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4)); -} - -/** - * @brief Get ADC analog watchdog threshold value of threshold high, - * threshold low or raw data with ADC thresholds high and low - * concatenated. - * @note If raw data with ADC thresholds high and low is retrieved, - * the data of each threshold high or low can be isolated - * using helper macro: - * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(). - * @note In case of ADC resolution different of 12 bits, - * analog watchdog thresholds data require a specific shift. - * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). - * @rmtoll AWD1TR HT1 LL_ADC_GetAnalogWDThresholds\n - * AWD2TR HT2 LL_ADC_GetAnalogWDThresholds\n - * AWD3TR HT3 LL_ADC_GetAnalogWDThresholds\n - * AWD1TR LT1 LL_ADC_GetAnalogWDThresholds\n - * AWD2TR LT2 LL_ADC_GetAnalogWDThresholds\n - * AWD3TR LT3 LL_ADC_GetAnalogWDThresholds - * @param ADCx ADC instance - * @param AWDy This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD1 - * @arg @ref LL_ADC_AWD2 - * @arg @ref LL_ADC_AWD3 - * @param AWDThresholdsHighLow This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH - * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) -{ - /* Set bits with content of parameter "AWDThresholdValue" with bits */ - /* position in register and register position depending on parameters */ - /* "AWDThresholdsHighLow" and "AWDy". */ - /* Parameters "AWDy" and "AWDThresholdValue" are used with masks because */ - /* containing other bits reserved for other purpose. */ - const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, - (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) - >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) - + ((ADC_AWD_CR3_REGOFFSET & AWDy) - >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); - - return (uint32_t)(READ_BIT(*preg, - (AWDThresholdsHighLow | ADC_AWD1TR_LT1)) - >> (((AWDThresholdsHighLow & ADC_AWD_TRX_BIT_HIGH_MASK) >> ADC_AWD_TRX_BIT_HIGH_SHIFT4) & ~ - (AWDThresholdsHighLow & ADC_AWD1TR_LT1)) - ); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_oversampling Configuration of ADC transversal scope: oversampling - * @{ - */ - -/** - * @brief Set ADC oversampling scope. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR2 OVSE LL_ADC_SetOverSamplingScope - * @param ADCx ADC instance - * @param OvsScope This parameter can be one of the following values: - * @arg @ref LL_ADC_OVS_DISABLE - * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t OvsScope) -{ - MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_OVSE, OvsScope); -} - -/** - * @brief Get ADC oversampling scope. - * @rmtoll CFGR2 OVSE LL_ADC_GetOverSamplingScope - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_OVS_DISABLE - * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED - */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); -} - -/** - * @brief Set ADC oversampling discontinuous mode (triggered mode) - * on the selected ADC group. - * @note Number of oversampled conversions are done either in: - * - continuous mode (all conversions of oversampling ratio - * are done from 1 trigger) - * - discontinuous mode (each conversion of oversampling ratio - * needs a trigger) - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR2 TOVS LL_ADC_SetOverSamplingDiscont - * @param ADCx ADC instance - * @param OverSamplingDiscont This parameter can be one of the following values: - * @arg @ref LL_ADC_OVS_REG_CONT - * @arg @ref LL_ADC_OVS_REG_DISCONT - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t OverSamplingDiscont) -{ - MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_TOVS, OverSamplingDiscont); -} - -/** - * @brief Get ADC oversampling discontinuous mode (triggered mode) - * on the selected ADC group. - * @note Number of oversampled conversions are done either in: - * - continuous mode (all conversions of oversampling ratio - * are done from 1 trigger) - * - discontinuous mode (each conversion of oversampling ratio - * needs a trigger) - * @rmtoll CFGR2 TOVS LL_ADC_GetOverSamplingDiscont - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_OVS_REG_CONT - * @arg @ref LL_ADC_OVS_REG_DISCONT - */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); -} - -/** - * @brief Set ADC oversampling - * @note This function set the 2 items of oversampling configuration: - * - ratio - * - shift - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR2 OVSS LL_ADC_ConfigOverSamplingRatioShift\n - * CFGR2 OVSR LL_ADC_ConfigOverSamplingRatioShift - * @param ADCx ADC instance - * @param Ratio This parameter can be one of the following values: - * @arg @ref LL_ADC_OVS_RATIO_2 - * @arg @ref LL_ADC_OVS_RATIO_4 - * @arg @ref LL_ADC_OVS_RATIO_8 - * @arg @ref LL_ADC_OVS_RATIO_16 - * @arg @ref LL_ADC_OVS_RATIO_32 - * @arg @ref LL_ADC_OVS_RATIO_64 - * @arg @ref LL_ADC_OVS_RATIO_128 - * @arg @ref LL_ADC_OVS_RATIO_256 - * @param Shift This parameter can be one of the following values: - * @arg @ref LL_ADC_OVS_SHIFT_NONE - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 - * @retval None - */ -__STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint32_t Ratio, uint32_t Shift) -{ - MODIFY_REG(ADCx->CFGR2, (ADC_CFGR2_OVSS | ADC_CFGR2_OVSR), (Shift | Ratio)); -} - -/** - * @brief Get ADC oversampling ratio - * @rmtoll CFGR2 OVSR LL_ADC_GetOverSamplingRatio - * @param ADCx ADC instance - * @retval Ratio This parameter can be one of the following values: - * @arg @ref LL_ADC_OVS_RATIO_2 - * @arg @ref LL_ADC_OVS_RATIO_4 - * @arg @ref LL_ADC_OVS_RATIO_8 - * @arg @ref LL_ADC_OVS_RATIO_16 - * @arg @ref LL_ADC_OVS_RATIO_32 - * @arg @ref LL_ADC_OVS_RATIO_64 - * @arg @ref LL_ADC_OVS_RATIO_128 - * @arg @ref LL_ADC_OVS_RATIO_256 - */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); -} - -/** - * @brief Get ADC oversampling shift - * @rmtoll CFGR2 OVSS LL_ADC_GetOverSamplingShift - * @param ADCx ADC instance - * @retval Shift This parameter can be one of the following values: - * @arg @ref LL_ADC_OVS_SHIFT_NONE - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_1 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_2 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_3 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_4 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_5 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_6 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 - * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 - */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance - * @{ - */ - -/** - * @brief Enable ADC instance internal voltage regulator. - * @note On this STM32 series, there are three possibilities to enable - * the voltage regulator: - * - by enabling it manually - * using function @ref LL_ADC_EnableInternalRegulator(). - * - by launching a calibration - * using function @ref LL_ADC_StartCalibration(). - * - by enabling the ADC - * using function @ref LL_ADC_Enable(). - * @note On this STM32 series, after ADC internal voltage regulator enable, - * a delay for ADC internal voltage regulator stabilization - * is required before performing a ADC calibration or ADC enable. - * Refer to device datasheet, parameter "tADCVREG_STUP". - * Refer to literal @ref LL_ADC_DELAY_INTERNAL_REGUL_STAB_US. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be ADC disabled. - * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, - ADC_CR_BITS_PROPERTY_RS, - ADC_CR_ADVREGEN); -} - -/** - * @brief Disable ADC internal voltage regulator. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be ADC disabled. - * @rmtoll CR ADVREGEN LL_ADC_DisableInternalRegulator - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->CR, (ADC_CR_ADVREGEN | ADC_CR_BITS_PROPERTY_RS)); -} - -/** - * @brief Get the selected ADC instance internal voltage regulator state. - * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled - * @param ADCx ADC instance - * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. - */ -__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable the selected ADC instance. - * @note On this STM32 series, after ADC enable, a delay for - * ADC internal analog stabilization is required before performing a - * ADC conversion start. - * Refer to device datasheet, parameter tSTAB. - * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC - * is enabled and when conversion clock is active. - * (not only core clock: this ADC has a dual clock domain) - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be ADC disabled and ADC internal voltage regulator enabled. - * @rmtoll CR ADEN LL_ADC_Enable - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, - ADC_CR_BITS_PROPERTY_RS, - ADC_CR_ADEN); -} - -/** - * @brief Disable the selected ADC instance. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be not disabled. Must be enabled without conversion on going - * on group regular. - * @rmtoll CR ADDIS LL_ADC_Disable - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, - ADC_CR_BITS_PROPERTY_RS, - ADC_CR_ADDIS); -} - -/** - * @brief Get the selected ADC instance enable state. - * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC - * is enabled and when conversion clock is active. - * (not only core clock: this ADC has a dual clock domain) - * @rmtoll CR ADEN LL_ADC_IsEnabled - * @param ADCx ADC instance - * @retval 0: ADC is disabled, 1: ADC is enabled. - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); -} - -/** - * @brief Get the selected ADC instance disable state. - * @rmtoll CR ADDIS LL_ADC_IsDisableOngoing - * @param ADCx ADC instance - * @retval 0: no ADC disable command on going. - */ -__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); -} - -/** - * @brief Start ADC calibration in the mode single-ended - * or differential (for devices with differential mode available). - * @note On this STM32 series, a minimum number of ADC clock cycles - * are required between ADC end of calibration and ADC enable. - * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. - * @note In case of usage of ADC with DMA transfer: - * On this STM32 series, ADC DMA transfer request should be disabled - * during calibration: - * Calibration factor is available in data register - * and also transferred by DMA. - * To not insert ADC calibration factor among ADC conversion data - * in array variable, DMA transfer must be disabled during - * calibration. - * (DMA transfer setting backup and disable before calibration, - * DMA transfer setting restore after calibration. - * Refer to functions @ref LL_ADC_REG_GetDMATransfer(), - * @ref LL_ADC_REG_SetDMATransfer() ). - * @note In case of usage of feature auto power-off: - * This mode must be disabled during calibration - * Refer to function @ref LL_ADC_SetLowPowerMode(). - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be ADC disabled. - * @rmtoll CR ADCAL LL_ADC_StartCalibration - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, - ADC_CR_BITS_PROPERTY_RS, - ADC_CR_ADCAL); -} - -/** - * @brief Get ADC calibration state. - * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing - * @param ADCx ADC instance - * @retval 0: calibration complete, 1: calibration in progress. - */ -__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular - * @{ - */ - -/** - * @brief Start ADC group regular conversion. - * @note On this STM32 series, this function is relevant for both - * internal trigger (SW start) and external trigger: - * - If ADC trigger has been set to software start, ADC conversion - * starts immediately. - * - If ADC trigger has been set to external trigger, ADC conversion - * will start at next trigger event (on the selected trigger edge) - * following the ADC start conversion command. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be enabled without conversion on going on group regular, - * without conversion stop command on going on group regular, - * without ADC disable command on going. - * @rmtoll CR ADSTART LL_ADC_REG_StartConversion - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, - ADC_CR_BITS_PROPERTY_RS, - ADC_CR_ADSTART); -} - -/** - * @brief Stop ADC group regular conversion. - * @note On this STM32 series, setting of this feature is conditioned to - * ADC state: - * ADC must be enabled with conversion on going on group regular, - * without ADC disable command on going. - * @rmtoll CR ADSTP LL_ADC_REG_StopConversion - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, - ADC_CR_BITS_PROPERTY_RS, - ADC_CR_ADSTP); -} - -/** - * @brief Get ADC group regular conversion state. - * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing - * @param ADCx ADC instance - * @retval 0: no conversion is on going on ADC group regular. - */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); -} - -/** - * @brief Get ADC group regular command of conversion stop state - * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing - * @param ADCx ADC instance - * @retval 0: no command of conversion stop is on going on ADC group regular. - */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * all ADC configurations: all ADC resolutions and - * all oversampling increased data width (for devices - * with feature oversampling). - * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 12 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx) -{ - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 10 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x000 and Max_Data=0x3FF - */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx) -{ - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 8 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) -{ - return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 6 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x00 and Max_Data=0x3F - */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx) -{ - return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management - * @{ - */ - -/** - * @brief Get flag ADC ready. - * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC - * is enabled and when conversion clock is active. - * (not only core clock: this ADC has a dual clock domain) - * @rmtoll ISR ADRDY LL_ADC_IsActiveFlag_ADRDY - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC channel configuration ready. - * @note On this STM32 series, after modifying sequencer - * it is mandatory to wait for the assertion of CCRDY flag - * using @ref LL_ADC_IsActiveFlag_CCRDY(). - * Otherwise, performing some actions (configuration update, - * ADC conversion start, ... ) will be ignored. - * Functions requiring wait for CCRDY flag are: - * @ref LL_ADC_REG_SetSequencerLength() - * @ref LL_ADC_REG_SetSequencerRanks() - * @ref LL_ADC_REG_SetSequencerChannels() - * @ref LL_ADC_REG_SetSequencerChAdd() - * @ref LL_ADC_REG_SetSequencerChRem() - * @ref LL_ADC_REG_SetSequencerScanDirection() - * @ref LL_ADC_REG_SetSequencerConfigurable() - * @note Duration of ADC channel configuration ready: CCRDY handshake - * requires 1APB + 2 ADC + 3 APB cycles after the channel configuration - * has been changed. - * @rmtoll ISR CCRDY LL_ADC_IsActiveFlag_CCRDY - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC group regular end of unitary conversion. - * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC group regular end of sequence conversions. - * @rmtoll ISR EOS LL_ADC_IsActiveFlag_EOS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC group regular overrun. - * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC group regular end of sampling phase. - * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC analog watchdog 1 flag - * @rmtoll ISR AWD1 LL_ADC_IsActiveFlag_AWD1 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC analog watchdog 2. - * @rmtoll ISR AWD2 LL_ADC_IsActiveFlag_AWD2 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC analog watchdog 3. - * @rmtoll ISR AWD3 LL_ADC_IsActiveFlag_AWD3 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); -} - -/** - * @brief Get flag ADC end of calibration. - * @rmtoll ISR EOCAL LL_ADC_IsActiveFlag_EOCAL - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL); -} - -/** - * @brief Clear flag ADC ready. - * @note On this STM32 series, flag LL_ADC_FLAG_ADRDY is raised when the ADC - * is enabled and when conversion clock is active. - * (not only core clock: this ADC has a dual clock domain) - * @rmtoll ISR ADRDY LL_ADC_ClearFlag_ADRDY - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_ADRDY(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_ADRDY); -} - -/** - * @brief Clear flag ADC channel configuration ready. - * @rmtoll ISR CCRDY LL_ADC_ClearFlag_CCRDY - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void LL_ADC_ClearFlag_CCRDY(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_CCRDY); -} - -/** - * @brief Clear flag ADC group regular end of unitary conversion. - * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC); -} - -/** - * @brief Clear flag ADC group regular end of sequence conversions. - * @rmtoll ISR EOS LL_ADC_ClearFlag_EOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS); -} - -/** - * @brief Clear flag ADC group regular overrun. - * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR); -} - -/** - * @brief Clear flag ADC group regular end of sampling phase. - * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP); -} - -/** - * @brief Clear flag ADC analog watchdog 1. - * @rmtoll ISR AWD1 LL_ADC_ClearFlag_AWD1 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_AWD1(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD1); -} - -/** - * @brief Clear flag ADC analog watchdog 2. - * @rmtoll ISR AWD2 LL_ADC_ClearFlag_AWD2 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_AWD2(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD2); -} - -/** - * @brief Clear flag ADC analog watchdog 3. - * @rmtoll ISR AWD3 LL_ADC_ClearFlag_AWD3 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_AWD3(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD3); -} - -/** - * @brief Clear flag ADC end of calibration. - * @rmtoll ISR EOCAL LL_ADC_ClearFlag_EOCAL - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_EOCAL(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOCAL); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_IT_Management ADC IT management - * @{ - */ - -/** - * @brief Enable ADC ready. - * @rmtoll IER ADRDYIE LL_ADC_EnableIT_ADRDY - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_ADRDY(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_ADRDY); -} - -/** - * @brief Enable interruption ADC channel configuration ready. - * @rmtoll IER ADRDYIE LL_ADC_EnableIT_CCRDY - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void LL_ADC_EnableIT_CCRDY(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY); -} - -/** - * @brief Enable interruption ADC group regular end of unitary conversion. - * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_EOC); -} - -/** - * @brief Enable interruption ADC group regular end of sequence conversions. - * @rmtoll IER EOSIE LL_ADC_EnableIT_EOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_EOS); -} - -/** - * @brief Enable ADC group regular interruption overrun. - * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_OVR); -} - -/** - * @brief Enable interruption ADC group regular end of sampling. - * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP); -} - -/** - * @brief Enable interruption ADC analog watchdog 1. - * @rmtoll IER AWD1IE LL_ADC_EnableIT_AWD1 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_AWD1(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_AWD1); -} - -/** - * @brief Enable interruption ADC analog watchdog 2. - * @rmtoll IER AWD2IE LL_ADC_EnableIT_AWD2 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_AWD2(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_AWD2); -} - -/** - * @brief Enable interruption ADC analog watchdog 3. - * @rmtoll IER AWD3IE LL_ADC_EnableIT_AWD3 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_AWD3(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_AWD3); -} -/** - * @brief Enable interruption ADC end of calibration. - * @rmtoll IER EOCALIE LL_ADC_EnableIT_EOCAL - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_EOCAL(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_EOCAL); -} - -/** - * @brief Disable interruption ADC ready. - * @rmtoll IER ADRDYIE LL_ADC_DisableIT_ADRDY - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_ADRDY(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_ADRDY); -} - -/** - * @brief Disable interruption ADC channel configuration ready. - * @rmtoll IER CCRDYIE LL_ADC_DisableIT_CCRDY - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE void LL_ADC_DisableIT_CCRDY(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY); -} - -/** - * @brief Disable interruption ADC group regular end of unitary conversion. - * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC); -} - -/** - * @brief Disable interruption ADC group regular end of sequence conversions. - * @rmtoll IER EOSIE LL_ADC_DisableIT_EOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS); -} - -/** - * @brief Disable interruption ADC group regular overrun. - * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR); -} - -/** - * @brief Disable interruption ADC group regular end of sampling. - * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP); -} - -/** - * @brief Disable interruption ADC analog watchdog 1. - * @rmtoll IER AWD1IE LL_ADC_DisableIT_AWD1 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_AWD1(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD1); -} - -/** - * @brief Disable interruption ADC analog watchdog 2. - * @rmtoll IER AWD2IE LL_ADC_DisableIT_AWD2 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_AWD2(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD2); -} - -/** - * @brief Disable interruption ADC analog watchdog 3. - * @rmtoll IER AWD3IE LL_ADC_DisableIT_AWD3 - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_AWD3(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD3); -} - -/** - * @brief Disable interruption ADC end of calibration. - * @rmtoll IER EOCALIE LL_ADC_DisableIT_EOCAL - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOCAL); -} - -/** - * @brief Get state of interruption ADC ready - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER ADRDYIE LL_ADC_IsEnabledIT_ADRDY - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption ADC channel configuration ready. - * @rmtoll IER CCRDYIE LL_ADC_IsEnabledIT_CCRDY - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption ADC group regular end of unitary conversion - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption ADC group regular end of sequence conversions - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER EOSIE LL_ADC_IsEnabledIT_EOS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption ADC group regular overrun - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption ADC group regular end of sampling - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption ADC analog watchdog 1 - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER AWD1IE LL_ADC_IsEnabledIT_AWD1 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption Get ADC analog watchdog 2 - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER AWD2IE LL_ADC_IsEnabledIT_AWD2 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption Get ADC analog watchdog 3 - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER AWD3IE LL_ADC_IsEnabledIT_AWD3 - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); -} - -/** - * @brief Get state of interruption ADC end of calibration - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER EOCALIE LL_ADC_IsEnabledIT_EOCAL - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx) -{ - return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -/* Initialization of some features of ADC common parameters and multimode */ -ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON); -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); -void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct); - -/* De-initialization of ADC instance */ -ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); -/* Initialization of some features of ADC instance */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *ADC_InitStruct); -void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); - -/* Initialization of some features of ADC instance and ADC group regular */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); -void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* ADC1 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* STM32C0xx_LL_ADC_H */ diff --git a/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c b/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c deleted file mode 100644 index c3c83e0..0000000 --- a/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc.c +++ /dev/null @@ -1,3066 +0,0 @@ -/** - ****************************************************************************** - * @file stm32c0xx_hal_adc.c - * @author MCD Application Team - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Converter (ADC) - * peripheral: - * + Initialization and de-initialization functions - * ++ Initialization and Configuration of ADC - * + Operation functions - * ++ Start, stop, get result of conversions of regular - * group, using 3 possible modes: polling, interruption or DMA. - * + Control functions - * ++ Channels configuration on regular group - * ++ Analog Watchdog configuration - * + State functions - * ++ ADC state machine management - * ++ Interrupts and flags management - * Other functions (extended functions) are available in file - * "stm32c0xx_hal_adc_ex.c". - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - ============================================================================== - ##### ADC peripheral features ##### - ============================================================================== - [..] - (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. - - (+) Interrupt generation at the end of regular conversion and in case of - analog watchdog or overrun events. - - (+) Single and continuous conversion modes. - - (+) Scan mode for conversion of several channels sequentially. - - (+) Data alignment with in-built data coherency. - - (+) Programmable sampling time (common to group of channels) - - (+) External trigger (timer or EXTI) with configurable polarity - - (+) DMA request generation for transfer of conversions data of regular group. - - (+) ADC calibration - - (+) ADC conversion of regular group. - - (+) ADC supply requirements: 1.62 V to 3.6 V. - - (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to - Vdda or to an external voltage reference). - - - ##### How to use this driver ##### - ============================================================================== - [..] - - *** Configuration of top level parameters related to ADC *** - ============================================================ - [..] - - (#) Enable the ADC interface - (++) As prerequisite, ADC clock must be configured at RCC top level. - Caution: On STM32C0, ADC clock frequency max is 35MHz (refer - to device datasheet). - Therefore, ADC clock source from RCC and ADC clock - prescaler must be configured to remain below - this maximum frequency. - - (++) Two clock settings are mandatory: - (+++) ADC clock (core clock, also possibly conversion clock). - - (+++) ADC clock (conversions clock). - Four possible clock sources: synchronous clock from APB clock (same as ADC core clock) - or asynchronous clock from RCC level: SYSCLK, HSI48. - - (+++) Example: - Into HAL_ADC_MspInit() (recommended code location) or with - other device clock parameters configuration: - (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory: core clock) - - (++) ADC clock source and clock prescaler are configured at ADC level with - parameter "ClockPrescaler" using function HAL_ADC_Init(). - - (#) ADC pins configuration - (++) Enable the clock for the ADC GPIOs - using macro __HAL_RCC_GPIOx_CLK_ENABLE() - (++) Configure these ADC pins in analog mode - using function HAL_GPIO_Init() - - (#) Optionally, in case of usage of ADC with interruptions: - (++) Configure the NVIC for ADC - using function HAL_NVIC_EnableIRQ(ADCx_IRQn) - (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() - into the function of corresponding ADC interruption vector - ADCx_IRQHandler(). - - (#) Optionally, in case of usage of DMA: - (++) Configure the DMA (DMA channel, mode normal or circular, ...) - using function HAL_DMA_Init(). - (++) Configure the NVIC for DMA - using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) - (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() - into the function of corresponding DMA interruption vector - DMAx_Channelx_IRQHandler(). - - *** Configuration of ADC, group regular, channels parameters *** - ================================================================ - [..] - - (#) Configure the ADC parameters (resolution, data alignment, ...) - and regular group parameters (conversion trigger, sequencer, ...) - using function HAL_ADC_Init(). - - (#) Configure the channels for regular group parameters (channel number, - channel rank into sequencer, ..., into regular group) - using function HAL_ADC_ConfigChannel(). - - (#) Optionally, configure the analog watchdog parameters (channels - monitored, thresholds, ...) - using function HAL_ADC_AnalogWDGConfig(). - - *** Execution of ADC conversions *** - ==================================== - [..] - - (#) Optionally, perform an automatic ADC calibration to improve the - conversion accuracy - using function HAL_ADCEx_Calibration_Start(). - - (#) ADC driver can be used among three modes: polling, interruption, - transfer by DMA. - - (++) ADC conversion by polling: - (+++) Activate the ADC peripheral and start conversions - using function HAL_ADC_Start() - (+++) Wait for ADC conversion completion - using function HAL_ADC_PollForConversion() - (+++) Retrieve conversion results - using function HAL_ADC_GetValue() - (+++) Stop conversion and disable the ADC peripheral - using function HAL_ADC_Stop() - - (++) ADC conversion by interruption: - (+++) Activate the ADC peripheral and start conversions - using function HAL_ADC_Start_IT() - (+++) Wait for ADC conversion completion by call of function - HAL_ADC_ConvCpltCallback() - (this function must be implemented in user program) - (+++) Retrieve conversion results - using function HAL_ADC_GetValue() - (+++) Stop conversion and disable the ADC peripheral - using function HAL_ADC_Stop_IT() - - (++) ADC conversion with transfer by DMA: - (+++) Activate the ADC peripheral and start conversions - using function HAL_ADC_Start_DMA() - (+++) Wait for ADC conversion completion by call of function - HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() - (these functions must be implemented in user program) - (+++) Conversion results are automatically transferred by DMA into - destination variable address. - (+++) Stop conversion and disable the ADC peripheral - using function HAL_ADC_Stop_DMA() - - [..] - - (@) Callback functions must be implemented in user program: - (+@) HAL_ADC_ErrorCallback() - (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) - (+@) HAL_ADC_ConvCpltCallback() - (+@) HAL_ADC_ConvHalfCpltCallback - - *** Deinitialization of ADC *** - ============================================================ - [..] - - (#) Disable the ADC interface - (++) ADC clock can be hard reset and disabled at RCC top level. - (++) Hard reset of ADC peripherals - using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). - (++) ADC clock disable - using the equivalent macro/functions as configuration step. - (+++) Example: - Into HAL_ADC_MspDeInit() (recommended code location) or with - other device clock parameters configuration: - (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; - (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock) - (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); - - (#) ADC pins configuration - (++) Disable the clock for the ADC GPIOs - using macro __HAL_RCC_GPIOx_CLK_DISABLE() - - (#) Optionally, in case of usage of ADC with interruptions: - (++) Disable the NVIC for ADC - using function HAL_NVIC_EnableIRQ(ADCx_IRQn) - - (#) Optionally, in case of usage of DMA: - (++) Deinitialize the DMA - using function HAL_DMA_Init(). - (++) Disable the NVIC for DMA - using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) - - [..] - - *** Callback registration *** - ============================================= - [..] - - The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, - allows the user to configure dynamically the driver callbacks. - Use Functions @ref HAL_ADC_RegisterCallback() - to register an interrupt callback. - [..] - - Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: - (+) ConvCpltCallback : ADC conversion complete callback - (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback - (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback - (+) ErrorCallback : ADC error callback - (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback - (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback - (+) EndOfSamplingCallback : ADC end of sampling callback - (+) MspInitCallback : ADC Msp Init callback - (+) MspDeInitCallback : ADC Msp DeInit callback - This function takes as parameters the HAL peripheral handle, the Callback ID - and a pointer to the user callback function. - [..] - - Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default - weak function. - [..] - - @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, - and the Callback ID. - This function allows to reset following callbacks: - (+) ConvCpltCallback : ADC conversion complete callback - (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback - (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback - (+) ErrorCallback : ADC error callback - (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback - (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback - (+) EndOfSamplingCallback : ADC end of sampling callback - (+) MspInitCallback : ADC Msp Init callback - (+) MspDeInitCallback : ADC Msp DeInit callback - [..] - - By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET - all callbacks are set to the corresponding weak functions: - examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). - Exception done for MspInit and MspDeInit functions that are - reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when - these callbacks are null (not registered beforehand). - [..] - - If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() - keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. - [..] - - Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. - Exception done MspInit/MspDeInit functions that can be registered/unregistered - in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, - thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. - [..] - - Then, the user first registers the MspInit/MspDeInit user callbacks - using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() - or @ref HAL_ADC_Init() function. - [..] - - When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or - not defined, the callback registration feature is not available and all callbacks - are set to the corresponding weak functions. - - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32c0xx_hal.h" - -/** @addtogroup STM32C0xx_HAL_Driver - * @{ - */ - -/** @defgroup ADC ADC - * @brief ADC HAL module driver - * @{ - */ - -#ifdef HAL_ADC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup ADC_Private_Constants ADC Private Constants - * @{ - */ - -/* Fixed timeout values for ADC calibration, enable settling time, disable */ -/* settling time. */ -/* Values defined to be higher than worst cases: low clock frequency, */ -/* maximum prescaler. */ -/* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock */ -/* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits. */ -/* Unit: ms */ -#define ADC_ENABLE_TIMEOUT (2UL) -#define ADC_DISABLE_TIMEOUT (2UL) -#define ADC_STOP_CONVERSION_TIMEOUT (2UL) -#define ADC_CHANNEL_CONF_RDY_TIMEOUT (1UL) - -/* Register CHSELR bits corresponding to ranks 2 to 8 . */ -#define ADC_CHSELR_SQ2_TO_SQ8 (ADC_CHSELR_SQ2 | ADC_CHSELR_SQ3 | ADC_CHSELR_SQ4 | \ - ADC_CHSELR_SQ5 | ADC_CHSELR_SQ6 | ADC_CHSELR_SQ7 | ADC_CHSELR_SQ8) - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup ADC_Private_Functions ADC Private Functions - * @{ - */ -static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); -static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); -static void ADC_DMAError(DMA_HandleTypeDef *hdma); -/** - * @} - */ - -/* Exported functions ---------------------------------------------------------*/ - -/** @defgroup ADC_Exported_Functions ADC Exported Functions - * @{ - */ - -/** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions - * @brief ADC Initialization and Configuration functions - * -@verbatim - =============================================================================== - ##### Initialization and de-initialization functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Initialize and configure the ADC. - (+) De-initialize the ADC. -@endverbatim - * @{ - */ - -/** - * @brief Initialize the ADC peripheral and regular group according to - * parameters specified in structure "ADC_InitTypeDef". - * @note As prerequisite, ADC clock must be configured at RCC top level - * (refer to description of RCC configuration for ADC - * in header of this file). - * @note Possibility to update parameters on the fly: - * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when - * coming from ADC state reset. Following calls to this function can - * be used to reconfigure some parameters of ADC_InitTypeDef - * structure on the fly, without modifying MSP configuration. If ADC - * MSP has to be modified again, HAL_ADC_DeInit() must be called - * before HAL_ADC_Init(). - * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure - * "ADC_InitTypeDef". - * @note This function configures the ADC within 2 scopes: scope of entire - * ADC and scope of regular group. For parameters details, see comments - * of structure "ADC_InitTypeDef". - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpCFGR1 = 0UL; - uint32_t tmpCFGR2 = 0UL; - uint32_t tmp_adc_reg_is_conversion_on_going; - __IO uint32_t wait_loop_index = 0UL; - - /* Check ADC handle */ - if (hadc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); - assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); - assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); - assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); - assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); - assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); - assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); - assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoPowerOff)); - assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon1)); - assert_param(IS_ADC_SAMPLE_TIME(hadc->Init.SamplingTimeCommon2)); - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); - - assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode)); - - if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) - { - assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); - - if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) - { - assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); - } - } - - /* ADC group regular discontinuous mode can be enabled only if */ - /* continuous mode is disabled. */ - assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); - - /* Actions performed only if ADC is coming from state reset: */ - /* - Initialization of ADC MSP */ - if (hadc->State == HAL_ADC_STATE_RESET) - { -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - /* Init the ADC Callback settings */ - hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ - hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ - hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ - hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ - hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */ - hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */ - hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */ - hadc->CalibrationCpltCallback = HAL_ADC_CalibrationCpltCallback; /* Legacy weak callback */ - hadc->ADCReadyCallback = HAL_ADC_ADCReadyCallback; /* Legacy weak callback */ - hadc->ChannelConfigReadyCallback = HAL_ADCEx_ChannelConfigReadyCallback; /* Legacy weak callback */ - - if (hadc->MspInitCallback == NULL) - { - hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ - } - - /* Init the low level hardware */ - hadc->MspInitCallback(hadc); -#else - /* Init the low level hardware */ - HAL_ADC_MspInit(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Initialize Lock */ - hadc->Lock = HAL_UNLOCKED; - } - - if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) - { - /* Enable ADC internal voltage regulator */ - LL_ADC_EnableInternalRegulator(hadc->Instance); - - /* Delay for ADC stabilization time */ - /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles, scaling in us split to not */ - /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))); - while (wait_loop_index != 0UL) - { - wait_loop_index--; - } - } - - /* Verification that ADC voltage regulator is correctly enabled, whether */ - /* or not ADC is coming from state reset (if any potential problem of */ - /* clocking, voltage regulator would not be enabled). */ - if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - tmp_hal_status = HAL_ERROR; - } - - /* Configuration of ADC parameters if previous preliminary actions are */ - /* correctly completed and if there is no conversion on going on regular */ - /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ - /* called to update a parameter on the fly). */ - tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - - if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - && (tmp_adc_reg_is_conversion_on_going == 0UL) - ) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_BUSY_INTERNAL); - - /* Configuration of common ADC parameters */ - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated only when ADC is disabled: */ - /* - Internal voltage regulator (no parameter in HAL ADC init structure) */ - /* - Clock configuration */ - /* - ADC resolution */ - /* - Oversampling */ - /* - discontinuous mode */ - /* - LowPowerAutoWait mode */ - /* - LowPowerAutoPowerOff mode */ - /* - continuous conversion mode */ - /* - overrun */ - /* - external trigger to start conversion */ - /* - external trigger polarity */ - /* - data alignment */ - /* - resolution */ - /* - scan direction */ - /* - DMA continuous request */ - /* - Trigger frequency mode */ - /* Note: If low power mode AutoPowerOff is enabled, ADC enable */ - /* and disable phases are performed automatically by hardware */ - /* (in this case, flag ADC_FLAG_RDY is not set). */ - if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - { - /* Some parameters of this register are not reset, since they are set */ - /* by other functions and must be kept in case of usage of this */ - /* function on the fly (update of a parameter of ADC_InitTypeDef */ - /* without needing to reconfigure all other ADC groups/channels */ - /* parameters): */ - /* - internal measurement paths: temperature sensor, Vref */ - /* (set into HAL_ADC_ConfigChannel() ) */ - - tmpCFGR1 |= (hadc->Init.Resolution | - ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | - ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | - ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | - ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | - hadc->Init.DataAlign | - ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) | - ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); - - /* Update setting of discontinuous mode only if continuous mode is disabled */ - if (hadc->Init.DiscontinuousConvMode == ENABLE) - { - if (hadc->Init.ContinuousConvMode == DISABLE) - { - /* Enable the selected ADC group regular discontinuous mode */ - tmpCFGR1 |= ADC_CFGR1_DISCEN; - } - else - { - /* ADC regular group discontinuous was intended to be enabled, */ - /* but ADC regular group modes continuous and sequencer discontinuous */ - /* cannot be enabled simultaneously. */ - - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - } - - /* Enable external trigger if trigger selection is different of software */ - /* start. */ - /* Note: This configuration keeps the hardware feature of parameter */ - /* ExternalTrigConvEdge "trigger edge none" equivalent to */ - /* software start. */ - if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) - { - tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | - hadc->Init.ExternalTrigConvEdge); - } - - /* Update ADC configuration register with previous settings */ - MODIFY_REG(hadc->Instance->CFGR1, - ADC_CFGR1_RES | - ADC_CFGR1_DISCEN | - ADC_CFGR1_CHSELRMOD | - ADC_CFGR1_AUTOFF | - ADC_CFGR1_WAIT | - ADC_CFGR1_CONT | - ADC_CFGR1_OVRMOD | - ADC_CFGR1_EXTSEL | - ADC_CFGR1_EXTEN | - ADC_CFGR1_ALIGN | - ADC_CFGR1_SCANDIR | - ADC_CFGR1_DMACFG, - tmpCFGR1); - - tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | - hadc->Init.TriggerFrequencyMode - ); - - if (hadc->Init.OversamplingMode == ENABLE) - { - tmpCFGR2 |= (ADC_CFGR2_OVSE | - (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | - hadc->Init.Oversampling.Ratio | - hadc->Init.Oversampling.RightBitShift | - hadc->Init.Oversampling.TriggeredMode - ); - } - - MODIFY_REG(hadc->Instance->CFGR2, - ADC_CFGR2_CKMODE | - ADC_CFGR2_LFTRIG | - ADC_CFGR2_OVSE | - ADC_CFGR2_OVSR | - ADC_CFGR2_OVSS | - ADC_CFGR2_TOVS, - tmpCFGR2); - - /* Configuration of ADC clock mode: asynchronous clock source */ - /* with selectable prescaler. */ - if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) && - ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) && - ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4)) - { - MODIFY_REG(ADC1_COMMON->CCR, - ADC_CCR_PRESC, - hadc->Init.ClockPrescaler & ADC_CCR_PRESC); - } - } - - /* Channel sampling time configuration */ - LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1); - LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2); - - /* Configuration of regular group sequencer: */ - /* - if scan mode is disabled, regular channels sequence length is set to */ - /* 0x00: 1 channel converted (channel on regular rank 1) */ - /* Parameter "NbrOfConversion" is discarded. */ - /* Note: Scan mode is not present by hardware on this device, but */ - /* emulated by software for alignment over all STM32 devices. */ - /* - if scan mode is enabled, regular channels sequence length is set to */ - /* parameter "NbrOfConversion". */ - /* Channels must be configured into each rank using function */ - /* "HAL_ADC_ConfigChannel()". */ - if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) - { - /* Set sequencer scan length by clearing ranks above rank 1 */ - /* and do not modify rank 1 value. */ - SET_BIT(hadc->Instance->CHSELR, - ADC_CHSELR_SQ2_TO_SQ8); - } - else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) - { - /* Set ADC group regular sequencer: */ - /* - Set ADC group regular sequencer to value memorized */ - /* in HAL ADC handle */ - /* Note: This value maybe be initialized at a unknown value, */ - /* therefore after the first call of "HAL_ADC_Init()", */ - /* each rank corresponding to parameter "NbrOfConversion" */ - /* must be set using "HAL_ADC_ConfigChannel()". */ - /* - Set sequencer scan length by clearing ranks above maximum rank */ - /* and do not modify other ranks value. */ - MODIFY_REG(hadc->Instance->CHSELR, - ADC_CHSELR_SQ_ALL, - (ADC_CHSELR_SQ2_TO_SQ8 << (((hadc->Init.NbrOfConversion - 1UL) * ADC_REGULAR_RANK_2) & 0x1FUL)) - | (hadc->ADCGroupRegularSequencerRanks) - ); - } - else - { - /* Nothing to do */ - } - /* Check back that ADC registers have effectively been configured to */ - /* ensure of no potential problem of ADC core peripheral clocking. */ - if (LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) - == hadc->Init.SamplingTimeCommon1) - { - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Set the ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_READY); - } - else - { - /* Update ADC state machine to error */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - tmp_hal_status = HAL_ERROR; - } - - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - tmp_hal_status = HAL_ERROR; - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Deinitialize the ADC peripheral registers to their default reset - * values, with deinitialization of the ADC MSP. - * @note For devices with several ADCs: reset of ADC common registers is done - * only if all ADCs sharing the same common group are disabled. - * (function "HAL_ADC_MspDeInit()" is also called under the same conditions: - * all ADC instances use the same core clock at RCC level, disabling - * the core clock reset all ADC instances). - * If this is not the case, reset of these common parameters reset is - * bypassed without error reporting: it can be the intended behavior in - * case of reset of a single ADC while the other ADCs sharing the same - * common group is still running. - * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: - * this saves more power by reducing leakage currents - * and is particularly interesting before entering MCU low-power modes. - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check ADC handle */ - if (hadc == NULL) - { - return HAL_ERROR; - } - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); - - /* Stop potential conversion on going, on regular group */ - tmp_hal_status = ADC_ConversionStop(hadc); - - /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmp_hal_status == HAL_OK) - { - /* Disable the ADC peripheral */ - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Change ADC state */ - hadc->State = HAL_ADC_STATE_READY; - } - - /* Disable ADC internal voltage regulator */ - LL_ADC_DisableInternalRegulator(hadc->Instance); - } - - /* Note: HAL ADC deInit is done independently of ADC conversion stop */ - /* and disable return status. In case of status fail, attempt to */ - /* perform deinitialization anyway and it is up user code in */ - /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */ - /* system RCC hard reset. */ - - /* ========== Reset ADC registers ========== */ - - /* Reset register IER */ - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | - ADC_IT_AWD1 | ADC_IT_OVR | - ADC_IT_EOS | ADC_IT_EOC | - ADC_IT_EOCAL | ADC_IT_EOSMP | ADC_IT_RDY)); - - /* Reset register ISR */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | - ADC_FLAG_AWD1 | ADC_FLAG_OVR | - ADC_FLAG_EOS | ADC_FLAG_EOC | - ADC_FLAG_EOCAL | ADC_FLAG_EOSMP | ADC_FLAG_RDY)); - - /* Reset register CR */ - /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ - /* "read-set": no direct reset applicable. */ - - /* Reset register CFGR1 */ - hadc->Instance->CFGR1 &= ~(ADC_CFGR1_AWD1CH | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL | ADC_CFGR1_DISCEN | - ADC_CFGR1_CHSELRMOD | ADC_CFGR1_AUTOFF | - ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD | - ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RES | - ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN); - - /* Reset register CFGR2 */ - /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ - /* already done above. */ - hadc->Instance->CFGR2 &= ~ADC_CFGR2_CKMODE; - - /* Reset register SMPR */ - hadc->Instance->SMPR &= ~ADC_SMPR_SMP1; - - /* Reset registers AWDxTR */ - hadc->Instance->AWD1TR &= ~(ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1); - hadc->Instance->AWD2TR &= ~(ADC_AWD2TR_HT2 | ADC_AWD2TR_LT2); - hadc->Instance->AWD3TR &= ~(ADC_AWD3TR_HT3 | ADC_AWD3TR_LT3); - - /* Reset register CHSELR */ - hadc->Instance->CHSELR &= ~(ADC_CHSELR_SQ_ALL); - - /* Reset register DR */ - /* bits in access mode read only, no direct reset applicable */ - - /* Reset register CCR */ - ADC1_COMMON->CCR &= ~(ADC_CCR_TSEN | ADC_CCR_VREFEN | ADC_CCR_PRESC); - - /* ========== Hard reset ADC peripheral ========== */ - /* Performs a global reset of the entire ADC peripheral: ADC state is */ - /* forced to a similar state after device power-on. */ - /* If needed, copy-paste and uncomment the following reset code into */ - /* function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */ - /* */ - /* __HAL_RCC_ADC1_FORCE_RESET() */ - /* __HAL_RCC_ADC1_RELEASE_RESET() */ - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - if (hadc->MspDeInitCallback == NULL) - { - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - } - - /* DeInit the low level hardware */ - hadc->MspDeInitCallback(hadc); -#else - /* DeInit the low level hardware */ - HAL_ADC_MspDeInit(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Reset HAL ADC handle variable */ - hadc->ADCGroupRegularSequencerRanks = 0x00000000UL; - - /* Set ADC error code to none */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Set ADC state */ - hadc->State = HAL_ADC_STATE_RESET; - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Initialize the ADC MSP. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_MspInit must be implemented in the user file. - */ -} - -/** - * @brief DeInitialize the ADC MSP. - * @param hadc ADC handle - * @note All ADC instances use the same core clock at RCC level, disabling - * the core clock reset all ADC instances). - * @retval None - */ -__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_MspDeInit must be implemented in the user file. - */ -} - -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) -/** - * @brief Register a User ADC Callback - * To be used instead of the weak predefined callback - * @param hadc Pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param CallbackID ID of the callback to be registered - * This parameter can be one of the following values: - * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID - * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID - * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID - * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID - * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID - * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID - * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID - * @param pCallback pointer to the Callback function - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, - pADC_CallbackTypeDef pCallback) -{ - HAL_StatusTypeDef status = HAL_OK; - - if (pCallback == NULL) - { - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - return HAL_ERROR; - } - - if ((hadc->State & HAL_ADC_STATE_READY) != 0UL) - { - switch (CallbackID) - { - case HAL_ADC_CONVERSION_COMPLETE_CB_ID : - hadc->ConvCpltCallback = pCallback; - break; - - case HAL_ADC_CONVERSION_HALF_CB_ID : - hadc->ConvHalfCpltCallback = pCallback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : - hadc->LevelOutOfWindowCallback = pCallback; - break; - - case HAL_ADC_ERROR_CB_ID : - hadc->ErrorCallback = pCallback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : - hadc->LevelOutOfWindow2Callback = pCallback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : - hadc->LevelOutOfWindow3Callback = pCallback; - break; - - case HAL_ADC_END_OF_SAMPLING_CB_ID : - hadc->EndOfSamplingCallback = pCallback; - break; - - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = pCallback; - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_ADC_STATE_RESET == hadc->State) - { - switch (CallbackID) - { - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = pCallback; - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = pCallback; - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -/** - * @brief Unregister a ADC Callback - * ADC callback is redirected to the weak predefined callback - * @param hadc Pointer to a ADC_HandleTypeDef structure that contains - * the configuration information for the specified ADC. - * @param CallbackID ID of the callback to be unregistered - * This parameter can be one of the following values: - * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID - * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID - * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID - * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID - * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID - * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID - * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID - * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID - * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) -{ - HAL_StatusTypeDef status = HAL_OK; - - if ((hadc->State & HAL_ADC_STATE_READY) != 0) - { - switch (CallbackID) - { - case HAL_ADC_CONVERSION_COMPLETE_CB_ID : - hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; - break; - - case HAL_ADC_CONVERSION_HALF_CB_ID : - hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : - hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; - break; - - case HAL_ADC_ERROR_CB_ID : - hadc->ErrorCallback = HAL_ADC_ErrorCallback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : - hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; - break; - - case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : - hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; - break; - - case HAL_ADC_END_OF_SAMPLING_CB_ID : - hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; - break; - - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else if (HAL_ADC_STATE_RESET == hadc->State) - { - switch (CallbackID) - { - case HAL_ADC_MSPINIT_CB_ID : - hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ - break; - - case HAL_ADC_MSPDEINIT_CB_ID : - hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ - break; - - default : - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - break; - } - } - else - { - /* Update the error code */ - hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; - - /* Return error status */ - status = HAL_ERROR; - } - - return status; -} - -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions - * @brief ADC IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Start conversion of regular group. - (+) Stop conversion of regular group. - (+) Poll for conversion complete on regular group. - (+) Poll for conversion event. - (+) Get result of regular channel conversion. - (+) Start conversion of regular group and enable interruptions. - (+) Stop conversion of regular group and disable interruptions. - (+) Handle ADC interrupt request - (+) Start conversion of regular group and enable DMA transfer. - (+) Stop conversion of regular group and disable ADC DMA transfer. -@endverbatim - * @{ - */ - -/** - * @brief Enable ADC, start conversion of regular group. - * @note Interruptions enabled in this function: None. - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Perform ADC enable and conversion start if no conversion is on going */ - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmp_hal_status = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, - HAL_ADC_STATE_REG_BUSY); - - /* Set ADC error code */ - /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Clear ADC group regular conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Enable conversion of regular group. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* Start ADC group regular conversion */ - LL_ADC_REG_StartConversion(hadc->Instance); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } - } - else - { - tmp_hal_status = HAL_BUSY; - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Stop ADC conversion of regular group (and injected channels in - * case of auto_injection mode), disable ADC peripheral. - * @note: ADC peripheral disable is forcing stop of potential - * conversion on injected group. If injected group is under use, it - * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Stop potential conversion on going, on ADC group regular */ - tmp_hal_status = ADC_ConversionStop(hadc); - - /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmp_hal_status == HAL_OK) - { - /* 2. Disable the ADC peripheral */ - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_READY); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Wait for regular group conversion to be completed. - * @note ADC conversion flags EOS (end of sequence) and EOC (end of - * conversion) are cleared by this function, with an exception: - * if low power feature "LowPowerAutoWait" is enabled, flags are - * not cleared to not interfere with this feature until data register - * is read using function HAL_ADC_GetValue(). - * @note This function cannot be used in a particular setup: ADC configured - * in DMA mode and polling for end of each conversion (ADC init - * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). - * In this case, DMA resets the flag EOC and polling cannot be - * performed on each conversion. Nevertheless, polling can still - * be performed on the complete sequence (ADC init - * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). - * @param hadc ADC handle - * @param Timeout Timeout value in millisecond. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout) -{ - uint32_t tickstart; - uint32_t tmp_Flag_End; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* If end of conversion selected to end of sequence conversions */ - if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) - { - tmp_Flag_End = ADC_FLAG_EOS; - } - /* If end of conversion selected to end of unitary conversion */ - else /* ADC_EOC_SINGLE_CONV */ - { - /* Verification that ADC configuration is compliant with polling for */ - /* each conversion: */ - /* Particular case is ADC configured in DMA mode and ADC sequencer with */ - /* several ranks and polling for end of each conversion. */ - /* For code simplicity sake, this particular case is generalized to */ - /* ADC configured in DMA mode and and polling for end of each conversion. */ - if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) != 0UL) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - return HAL_ERROR; - } - else - { - tmp_Flag_End = (ADC_FLAG_EOC); - } - } - - /* Get tick count */ - tickstart = HAL_GetTick(); - - /* Wait until End of unitary conversion or sequence conversions flag is raised */ - while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL) - { - /* Check if timeout is disabled (set to infinite wait) */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going. */ - if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) - && (hadc->Init.ContinuousConvMode == DISABLE) - ) - { - /* Check whether end of sequence is reached */ - if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) - { - /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ - /* ADSTART==0 (no conversion on going) */ - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* Disable ADC end of single conversion interrupt on group regular */ - /* Note: Overrun interrupt was enabled with EOC interrupt in */ - /* HAL_Start_IT(), but is not disabled here because can be used */ - /* by overrun IRQ process below. */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_READY); - } - else - { - /* Change ADC state to error state */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - } - } - - /* Clear end of conversion flag of regular group if low power feature */ - /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ - /* until data register is read using function HAL_ADC_GetValue(). */ - if (hadc->Init.LowPowerAutoWait == DISABLE) - { - /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Poll for ADC event. - * @param hadc ADC handle - * @param EventType the ADC event type. - * This parameter can be one of the following values: - * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event - * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on - * all STM32 devices) - * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on - * all STM32 families) - * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on - * all STM32 families) - * @arg @ref ADC_OVR_EVENT ADC Overrun event - * @param Timeout Timeout value in millisecond. - * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. - * Indeed, the latter is reset only if hadc->Init.Overrun field is set - * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten - * by a new converted data as soon as OVR is cleared. - * To reset OVR flag once the preserved data is retrieved, the user can resort - * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_EVENT_TYPE(EventType)); - - /* Get tick count */ - tickstart = HAL_GetTick(); - - /* Check selected event flag */ - while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL) - { - /* Check if timeout is disabled (set to infinite wait) */ - if (Timeout != HAL_MAX_DELAY) - { - if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL)) - { - /* Update ADC state machine to timeout */ - SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - return HAL_TIMEOUT; - } - } - } - - switch (EventType) - { - /* End Of Sampling event */ - case ADC_EOSMP_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); - - /* Clear the End Of Sampling flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); - - break; - - /* Analog watchdog (level out of window) event */ - /* Note: In case of several analog watchdog enabled, if needed to know */ - /* which one triggered and on which ADCx, test ADC state of analog watchdog */ - /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ - /* For example: */ - /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */ - /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */ - /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */ - - /* Check analog watchdog 1 flag */ - case ADC_AWD_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); - - break; - - /* Check analog watchdog 2 flag */ - case ADC_AWD2_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); - - break; - - /* Check analog watchdog 3 flag */ - case ADC_AWD3_EVENT: - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); - - break; - - /* Overrun event */ - default: /* Case ADC_OVR_EVENT */ - /* If overrun is set to overwrite previous data, overrun event is not */ - /* considered as an error. */ - /* (cf ref manual "Managing conversions without using the DMA and without */ - /* overrun ") */ - if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - - /* Set ADC error code to overrun */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - } - else - { - /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN - otherwise, data register is potentially overwritten by new converted data as soon - as OVR is cleared. */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - } - break; - } - - /* Return function status */ - return HAL_OK; -} - -/** - * @brief Enable ADC, start conversion of regular group with interruption. - * @note Interruptions enabled in this function according to initialization - * setting : EOC (end of conversion), EOS (end of sequence), - * OVR overrun. - * Each of these interruptions has its dedicated callback function. - * @note To guarantee a proper reset of all interruptions once all the needed - * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure - * a correct stop of the IT-based conversions. - * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling - * interruption. If required (e.g. in case of oversampling with trigger - * mode), the user must: - * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) - * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) - * before calling HAL_ADC_Start_IT(). - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Perform ADC enable and conversion start if no conversion is on going */ - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* Process locked */ - __HAL_LOCK(hadc); - - /* Enable the ADC peripheral */ - tmp_hal_status = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, - HAL_ADC_STATE_REG_BUSY); - - - /* Set ADC error code */ - /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Clear ADC group regular conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Disable all interruptions before enabling the desired ones */ - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - - /* Enable ADC end of conversion interrupt */ - switch (hadc->Init.EOCSelection) - { - case ADC_EOC_SEQ_CONV: - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); - break; - /* case ADC_EOC_SINGLE_CONV */ - default: - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); - break; - } - - /* Enable ADC overrun interrupt */ - /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is - ADC_IT_OVR enabled; otherwise data overwrite is considered as normal - behavior and no CPU time is lost for a non-processed interruption */ - if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) - { - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - } - - /* Enable conversion of regular group. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* Start ADC group regular conversion */ - LL_ADC_REG_StartConversion(hadc->Instance); - } - else - { - /* Process unlocked */ - __HAL_UNLOCK(hadc); - } - - } - else - { - tmp_hal_status = HAL_BUSY; - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable interrution of - * end-of-conversion, disable ADC peripheral. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Stop potential conversion on going, on ADC group regular */ - tmp_hal_status = ADC_ConversionStop(hadc); - - /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmp_hal_status == HAL_OK) - { - /* Disable ADC end of conversion interrupt for regular group */ - /* Disable ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); - - /* 2. Disable the ADC peripheral */ - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_READY); - } - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Enable ADC, start conversion of regular group and transfer result through DMA. - * @note Interruptions enabled in this function: - * overrun (if applicable), DMA half transfer, DMA transfer complete. - * Each of these interruptions has its dedicated callback function. - * @param hadc ADC handle - * @param pData Destination Buffer address. - * @param Length Number of data to be transferred from ADC peripheral to memory - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Perform ADC enable and conversion start if no conversion is on going */ - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* Process locked */ - __HAL_LOCK(hadc); - - /* Specific case for first call occurrence of this function (DMA transfer */ - /* not activated and ADC disabled), DMA transfer must be activated */ - /* with ADC disabled. */ - if ((hadc->Instance->CFGR1 & ADC_CFGR1_DMAEN) == 0UL) - { - if (LL_ADC_IsEnabled(hadc->Instance) != 0UL) - { - /* Disable ADC */ - LL_ADC_Disable(hadc->Instance); - } - - /* Enable ADC DMA mode */ - hadc->Instance->CFGR1 |= ADC_CFGR1_DMAEN; - } - - /* Enable the ADC peripheral */ - tmp_hal_status = ADC_Enable(hadc); - - /* Start conversion if ADC is effectively enabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - /* - Clear state bitfield related to regular group conversion results */ - /* - Set state bitfield related to regular operation */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, - HAL_ADC_STATE_REG_BUSY); - - /* Set ADC error code */ - /* Reset all ADC error code fields */ - ADC_CLEAR_ERRORCODE(hadc); - - /* Set the DMA transfer complete callback */ - hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; - - /* Set the DMA half transfer complete callback */ - hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; - - /* Set the DMA error callback */ - hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; - - - /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ - /* start (in case of SW start): */ - - /* Clear regular group conversion flag and overrun flag */ - /* (To ensure of no unknown state from potential previous ADC */ - /* operations) */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); - - /* Process unlocked */ - /* Unlock before starting ADC conversions: in case of potential */ - /* interruption, to let the process to ADC IRQ Handler. */ - __HAL_UNLOCK(hadc); - - /* Enable ADC overrun interrupt */ - __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); - - /* Start the DMA channel */ - tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); - - /* Enable conversion of regular group. */ - /* If software start has been selected, conversion starts immediately. */ - /* If external trigger has been selected, conversion will start at next */ - /* trigger event. */ - /* Start ADC group regular conversion */ - LL_ADC_REG_StartConversion(hadc->Instance); - } - } - else - { - tmp_hal_status = HAL_BUSY; - } - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Stop ADC conversion of regular group (and injected group in - * case of auto_injection mode), disable ADC DMA transfer, disable - * ADC peripheral. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* 1. Stop potential ADC group regular conversion on going */ - tmp_hal_status = ADC_ConversionStop(hadc); - - /* Disable ADC peripheral if conversions are effectively stopped */ - if (tmp_hal_status == HAL_OK) - { - /* Disable the DMA channel (in case of DMA in circular mode or stop */ - /* while DMA transfer is on going) */ - if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY) - { - tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); - - /* Check if DMA channel effectively disabled */ - if (tmp_hal_status != HAL_OK) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - } - } - - /* Disable ADC overrun interrupt */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); - - /* 2. Disable the ADC peripheral */ - /* Update "tmp_hal_status" only if DMA channel disabling passed, */ - /* to keep in memory a potential failing status. */ - if (tmp_hal_status == HAL_OK) - { - tmp_hal_status = ADC_Disable(hadc); - } - else - { - (void)ADC_Disable(hadc); - } - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_READY); - } - - /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */ - CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN); - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Get ADC regular group conversion result. - * @note Reading register DR automatically clears ADC flag EOC - * (ADC group regular end of unitary conversion). - * @note This function does not clear ADC flag EOS - * (ADC group regular end of sequence conversion). - * Occurrence of flag EOS rising: - * - If sequencer is composed of 1 rank, flag EOS is equivalent - * to flag EOC. - * - If sequencer is composed of several ranks, during the scan - * sequence flag EOC only is raised, at the end of the scan sequence - * both flags EOC and EOS are raised. - * To clear this flag, either use function: - * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming - * model polling: @ref HAL_ADC_PollForConversion() - * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). - * @param hadc ADC handle - * @retval ADC group regular conversion data - */ -uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Note: EOC flag is not cleared here by software because automatically */ - /* cleared by hardware when reading register DR. */ - - /* Return ADC converted value */ - return hadc->Instance->DR; -} - -/** - * @brief Handle ADC interrupt request. - * @param hadc ADC handle - * @retval None - */ -void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc) -{ - uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */ - uint32_t tmp_isr = hadc->Instance->ISR; - uint32_t tmp_ier = hadc->Instance->IER; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); - - /* ========== Check End of Sampling flag for ADC group regular ========== */ - if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) - { - /* Update state machine on end of sampling status if not in error state */ - if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); - } - - /* End Of Sampling callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->EndOfSamplingCallback(hadc); -#else - HAL_ADCEx_EndOfSamplingCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear regular group conversion flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); - } - - /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */ - if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || - (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS))) - { - /* Update state machine on conversion status if not in error state */ - if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - } - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going */ - /* to disable interruption. */ - if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) - && (hadc->Init.ContinuousConvMode == DISABLE) - ) - { - /* If End of Sequence is reached, disable interrupts */ - if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) - { - /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ - /* ADSTART==0 (no conversion on going) */ - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* Disable ADC end of single conversion interrupt on group regular */ - /* Note: Overrun interrupt was enabled with EOC interrupt in */ - /* HAL_Start_IT(), but is not disabled here because can be used */ - /* by overrun IRQ process below. */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_READY); - } - else - { - /* Change ADC state to error state */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - } - } - - /* Conversion complete callback */ - /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ - /* to determine if conversion has been triggered from EOC or EOS, */ - /* possibility to use: */ - /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ConvCpltCallback(hadc); -#else - HAL_ADC_ConvCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear regular group conversion flag */ - /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ - /* conversion flags clear induces the release of the preserved data.*/ - /* Therefore, if the preserved data value is needed, it must be */ - /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); - } - - /* ========== Check Analog watchdog 1 flag ========== */ - if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Level out of window 1 callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->LevelOutOfWindowCallback(hadc); -#else - HAL_ADC_LevelOutOfWindowCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); - } - - /* ========== Check analog watchdog 2 flag ========== */ - if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); - - /* Level out of window 2 callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->LevelOutOfWindow2Callback(hadc); -#else - HAL_ADCEx_LevelOutOfWindow2Callback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); - } - - /* ========== Check analog watchdog 3 flag ========== */ - if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); - - /* Level out of window 3 callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->LevelOutOfWindow3Callback(hadc); -#else - HAL_ADCEx_LevelOutOfWindow3Callback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); - } - /* ========== Check Overrun flag ========== */ - if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) - { - /* If overrun is set to overwrite previous data (default setting), */ - /* overrun event is not considered as an error. */ - /* (cf ref manual "Managing conversions without using the DMA and without */ - /* overrun ") */ - /* Exception for usage with DMA overrun event always considered as an */ - /* error. */ - if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) - { - overrun_error = 1UL; - } - else - { - /* Check DMA configuration */ - if (LL_ADC_REG_GetDMATransfer(hadc->Instance) != LL_ADC_REG_DMA_TRANSFER_NONE) - { - overrun_error = 1UL; - } - } - - if (overrun_error == 1UL) - { - /* Change ADC state to error state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); - - /* Set ADC error code to overrun */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); - - /* Error callback */ - /* Note: In case of overrun, ADC conversion data is preserved until */ - /* flag OVR is reset. */ - /* Therefore, old ADC conversion data can be retrieved in */ - /* function "HAL_ADC_ErrorCallback()". */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ErrorCallback(hadc); -#else - HAL_ADC_ErrorCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - } - - /* Clear ADC overrun flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); - } - - /* ========== Check ADC Ready flag ========== */ - if (((tmp_isr & ADC_FLAG_RDY) == ADC_FLAG_RDY) && ((tmp_ier & ADC_IT_RDY) == ADC_IT_RDY)) - { - /* Update state machine on end of sampling status if not in error state */ - if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_READY); - } - - /* ADC Ready callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ADCReadyCallback(hadc); -#else - HAL_ADC_ADCReadyCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Leave ADRDY flag up (used by HAL), disable interrupt source instead */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_RDY); - } - - /* ========== Check End of Calibration flag ========== */ - if (((tmp_isr & ADC_FLAG_EOCAL) == ADC_FLAG_EOCAL) && ((tmp_ier & ADC_IT_EOCAL) == ADC_IT_EOCAL)) - { - /* End Of Calibration callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->CalibrationCpltCallback(hadc); -#else - HAL_ADC_CalibrationCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear end of calibration flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOCAL); - } - - /* ========== Check channel configuration ready flag ========== */ - if (((tmp_isr & ADC_FLAG_CCRDY) == ADC_FLAG_CCRDY) && ((tmp_ier & ADC_IT_CCRDY) == ADC_IT_CCRDY)) - { - /* Channel configuration ready callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ChannelConfigReadyCallback(hadc); -#else - HAL_ADCEx_ChannelConfigReadyCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - - /* Clear ADC analog watchdog flag */ - __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_CCRDY); - } -} - -/** - * @brief Conversion complete callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ConvCpltCallback must be implemented in the user file. - */ -} - -/** - * @brief Conversion DMA half-transfer callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. - */ -} - -/** - * @brief Analog watchdog 1 callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. - */ -} - -/** - * @brief ADC error callback in non-blocking mode - * (ADC conversion with interruption or transfer by DMA). - * @note In case of error due to overrun when using ADC with DMA transfer - * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"): - * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". - * - If needed, restart a new ADC conversion using function - * "HAL_ADC_Start_DMA()" - * (this function is also clearing overrun flag) - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ErrorCallback must be implemented in the user file. - */ -} - -/** - * @brief Calibration complete callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_CalibrationCpltCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_CalibrationCpltCallback must be implemented in the user file. - */ -} - -/** - * @brief ADC Ready callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADC_ADCReadyCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADC_ADCReadyCallback must be implemented in the user file. - */ -} - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions - * @brief Peripheral Control functions - * -@verbatim - =============================================================================== - ##### Peripheral Control functions ##### - =============================================================================== - [..] This section provides functions allowing to: - (+) Configure channels on regular group - (+) Configure the analog watchdog - -@endverbatim - * @{ - */ - -/** - * @brief Configure a channel to be assigned to ADC group regular. - * @note In case of usage of internal measurement channels: - * VrefInt/TempSensor. - * These internal paths can be disabled using function - * HAL_ADC_DeInit(). - * @note Possibility to update parameters on the fly: - * This function initializes channel into ADC group regular, - * following calls to this function can be used to reconfigure - * some parameters of structure "ADC_ChannelConfTypeDef" on the fly, - * without resetting the ADC. - * The setting of these parameters is conditioned to ADC state: - * Refer to comments of structure "ADC_ChannelConfTypeDef". - * @param hadc ADC handle - * @param sConfig Structure of ADC channel assigned to ADC group regular. - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *sConfig) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmp_config_internal_channel; - __IO uint32_t wait_loop_index = 0UL; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CHANNEL(sConfig->Channel)); - assert_param(IS_ADC_SAMPLING_TIME_COMMON(sConfig->SamplingTime)); - - if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || - (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) - { - assert_param(IS_ADC_REGULAR_RANK_SEQ_FIXED(sConfig->Rank)); - } - else - { - assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); - - assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on regular group: */ - /* - Channel number */ - /* - Channel sampling time */ - /* - Management of internal measurement channels: VrefInt/TempSensor */ - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* Configure channel: depending on rank setting, add it or remove it from */ - /* ADC sequencer. */ - /* If sequencer set to not fully configurable with channel rank set to */ - /* none, remove the channel from the sequencer. */ - /* Otherwise (sequencer set to fully configurable or to to not fully */ - /* configurable with channel rank to be set), configure the selected */ - /* channel. */ - if (sConfig->Rank != ADC_RANK_NONE) - { - /* Regular sequence configuration */ - /* Note: ADC channel configuration requires few ADC clock cycles */ - /* to be ready. Processing of ADC settings in this function */ - /* induce that a specific wait time is not necessary. */ - /* For more details on ADC channel configuration ready, */ - /* refer to function "LL_ADC_IsActiveFlag_CCRDY()". */ - if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || - (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) - { - /* Sequencer set to not fully configurable: */ - /* Set the channel by enabling the corresponding bitfield. */ - LL_ADC_REG_SetSequencerChAdd(hadc->Instance, sConfig->Channel); - } - else - { - /* Sequencer set to fully configurable: */ - /* Set the channel by entering it into the selected rank. */ - - /* Memorize the channel set into variable in HAL ADC handle */ - MODIFY_REG(hadc->ADCGroupRegularSequencerRanks, - ADC_CHSELR_SQ1 << (sConfig->Rank & 0x1FUL), - __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) << (sConfig->Rank & 0x1FUL)); - - /* If the selected rank is below ADC group regular sequencer length, */ - /* apply the configuration in ADC register. */ - /* Note: Otherwise, configuration is not applied. */ - /* To apply it, parameter'NbrOfConversion' must be increased. */ - if (((sConfig->Rank >> 2UL) + 1UL) <= hadc->Init.NbrOfConversion) - { - LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); - } - } - - /* Set sampling time of the selected ADC channel */ - LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); - - /* Management of internal measurement channels: VrefInt/TempSensor */ - /* internal measurement paths enable: If internal channel selected, */ - /* enable dedicated internal buffers and path. */ - /* Note: these internal measurement paths can be disabled using */ - /* HAL_ADC_DeInit() or removing the channel from sequencer with */ - /* channel configuration parameter "Rank". */ - if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) - { - tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - - /* If the requested internal measurement path has already been enabled, */ - /* bypass the configuration processing. */ - if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && - ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel); - - /* Delay for temperature sensor stabilization time */ - /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles, scaling in us split to not */ - /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = (((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * (SystemCoreClock / (100000UL * 2UL))) + 1UL); - while (wait_loop_index != 0UL) - { - wait_loop_index--; - } - } - else if ((sConfig->Channel == ADC_CHANNEL_VREFINT) && - ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL)) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel); - } - else - { - /* nothing to do */ - } - } - } - else - { - /* Regular sequencer configuration */ - /* Note: Case of sequencer set to fully configurable: */ - /* Sequencer rank cannot be disabled, only affected to */ - /* another channel. */ - /* To remove a rank, use parameter 'NbrOfConversion". */ - if ((hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED) || - (hadc->Init.ScanConvMode == ADC_SCAN_SEQ_FIXED_BACKWARD)) - { - /* Sequencer set to not fully configurable: */ - /* Reset the channel by disabling the corresponding bitfield. */ - LL_ADC_REG_SetSequencerChRem(hadc->Instance, sConfig->Channel); - } - - /* Management of internal measurement channels: VrefInt/TempSensor. */ - /* If internal channel selected, enable dedicated internal buffers and */ - /* paths. */ - if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel)) - { - tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - - if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - ~LL_ADC_PATH_INTERNAL_TEMPSENSOR & tmp_config_internal_channel); - } - else if (sConfig->Channel == ADC_CHANNEL_VREFINT) - { - LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), - ~LL_ADC_PATH_INTERNAL_VREFINT & tmp_config_internal_channel); - } - else - { - /* nothing to do */ - } - } - } - } - - /* If a conversion is on going on regular group, no update on regular */ - /* channel could be done on neither of the channel configuration structure */ - /* parameters. */ - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - tmp_hal_status = HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Configure the analog watchdog. - * @note Possibility to update parameters on the fly: - * This function initializes the selected analog watchdog, successive - * calls to this function can be used to reconfigure some parameters - * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting - * the ADC. - * The setting of these parameters is conditioned to ADC state. - * For parameters constraints, see comments of structure - * "ADC_AnalogWDGConfTypeDef". - * @note On this STM32 series, analog watchdog thresholds can be modified - * while ADC conversion is on going. - * In this case, some constraints must be taken into account: - * the programmed threshold values are effective from the next - * ADC EOC (end of unitary conversion). - * Considering that registers write delay may happen due to - * bus activity, this might cause an uncertainty on the - * effective timing of the new programmed threshold values. - * @param hadc ADC handle - * @param AnalogWDGConfig Structure of ADC analog watchdog configuration - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, const ADC_AnalogWDGConfTypeDef *AnalogWDGConfig) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmpAWDHighThresholdShifted; - uint32_t tmpAWDLowThresholdShifted; - uint32_t backup_setting_adc_enable_state = 0UL; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber)); - assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); - assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); - - if (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) - { - assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel)); - } - - /* Verify thresholds range */ - if (hadc->Init.OversamplingMode == ENABLE) - { - /* Case of oversampling enabled: depending on ratio and shift configuration, - analog watchdog thresholds can be higher than ADC resolution. - Verify if thresholds are within maximum thresholds range. */ - assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold)); - } - else - { - /* Verify if thresholds are within the selected ADC resolution */ - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); - assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); - } - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Parameters update conditioned to ADC state: */ - /* Parameters that can be updated when ADC is disabled or enabled without */ - /* conversion on going on ADC group regular: */ - /* - Analog watchdog channels */ - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* Analog watchdog configuration */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) - { - /* Constraint of ADC on this STM32 series: ADC must be disable - to modify bitfields of register ADC_CFGR1 */ - if (LL_ADC_IsEnabled(hadc->Instance) != 0UL) - { - backup_setting_adc_enable_state = 1UL; - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (tmp_hal_status == HAL_OK) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_READY); - } - } - - /* Configuration of analog watchdog: */ - /* - Set the analog watchdog enable mode: one or overall group of */ - /* channels. */ - switch (AnalogWDGConfig->WatchdogMode) - { - case ADC_ANALOGWATCHDOG_SINGLE_REG: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, - __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, - LL_ADC_GROUP_REGULAR)); - break; - - case ADC_ANALOGWATCHDOG_ALL_REG: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG); - break; - - default: /* ADC_ANALOGWATCHDOG_NONE */ - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE); - break; - } - - if (backup_setting_adc_enable_state == 1UL) - { - tmp_hal_status = ADC_Enable(hadc); - } - - /* Update state, clear previous result related to AWD1 */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); - - /* Clear flag ADC analog watchdog */ - /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ - /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ - /* (in case left enabled by previous ADC operations). */ - LL_ADC_ClearFlag_AWD1(hadc->Instance); - - /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) - { - LL_ADC_EnableIT_AWD1(hadc->Instance); - } - else - { - LL_ADC_DisableIT_AWD1(hadc->Instance); - } - } - /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ - else - { - switch (AnalogWDGConfig->WatchdogMode) - { - case ADC_ANALOGWATCHDOG_SINGLE_REG: - /* Update AWD by bitfield to keep the possibility to monitor */ - /* several channels by successive calls of this function. */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) - { - SET_BIT(hadc->Instance->AWD2CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); - } - else - { - SET_BIT(hadc->Instance->AWD3CR, (1UL << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); - } - break; - - case ADC_ANALOGWATCHDOG_ALL_REG: - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG); - break; - - default: /* ADC_ANALOGWATCHDOG_NONE */ - LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); - break; - } - - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) - { - /* Update state, clear previous result related to AWD2 */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); - - /* Clear flag ADC analog watchdog */ - /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ - /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ - /* (in case left enabled by previous ADC operations). */ - LL_ADC_ClearFlag_AWD2(hadc->Instance); - - /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) - { - LL_ADC_EnableIT_AWD2(hadc->Instance); - } - else - { - LL_ADC_DisableIT_AWD2(hadc->Instance); - } - } - /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ - else - { - /* Update state, clear previous result related to AWD3 */ - CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); - - /* Clear flag ADC analog watchdog */ - /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ - /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ - /* (in case left enabled by previous ADC operations). */ - LL_ADC_ClearFlag_AWD3(hadc->Instance); - - /* Configure ADC analog watchdog interrupt */ - if (AnalogWDGConfig->ITMode == ENABLE) - { - LL_ADC_EnableIT_AWD3(hadc->Instance); - } - else - { - LL_ADC_DisableIT_AWD3(hadc->Instance); - } - } - } - - } - - /* Analog watchdog thresholds configuration */ - if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) - { - /* Shift the offset with respect to the selected ADC resolution: */ - /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ - /* are set to 0. */ - tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); - tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); - } - /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */ - else - { - /* No need to shift the offset with respect to the selected ADC resolution: */ - /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ - /* are set to 0. */ - tmpAWDHighThresholdShifted = AnalogWDGConfig->HighThreshold; - tmpAWDLowThresholdShifted = AnalogWDGConfig->LowThreshold; - } - - /* Set ADC analog watchdog thresholds value of both thresholds high and low */ - LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, - tmpAWDLowThresholdShifted); - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - - -/** - * @} - */ - -/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions - * @brief ADC Peripheral State functions - * -@verbatim - =============================================================================== - ##### Peripheral state and errors functions ##### - =============================================================================== - [..] - This subsection provides functions to get in run-time the status of the - peripheral. - (+) Check the ADC state - (+) Check the ADC error code - -@endverbatim - * @{ - */ - -/** - * @brief Return the ADC handle state. - * @note ADC state machine is managed by bitfields, ADC status must be - * compared with states bits. - * For example: - * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) " - * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " - * @param hadc ADC handle - * @retval ADC handle state (bitfield on 32 bits) - */ -uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Return ADC handle state */ - return hadc->State; -} - -/** - * @brief Return the ADC error code. - * @param hadc ADC handle - * @retval ADC error code (bitfield on 32 bits) - */ -uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - return hadc->ErrorCode; -} - -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup ADC_Private_Functions ADC Private Functions - * @{ - */ - -/** - * @brief Stop ADC conversion. - * @note Prerequisite condition to use this function: ADC conversions must be - * stopped to disable the ADC. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc) -{ - uint32_t tickstart; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Verification if ADC is not already stopped on regular group to bypass */ - /* this function if not needed. */ - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL) - { - /* Stop potential conversion on going on regular group */ - /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ - if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL) - { - /* Stop ADC group regular conversion */ - LL_ADC_REG_StopConversion(hadc->Instance); - } - - /* Wait for conversion effectively stopped */ - /* Get tick count */ - tickstart = HAL_GetTick(); - - while ((hadc->Instance->CR & ADC_CR_ADSTART) != 0UL) - { - if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - } - - } - - /* Return HAL status */ - return HAL_OK; -} - -/** - * @brief Enable the selected ADC. - * @note Prerequisite condition to use this function: ADC must be disabled - * and voltage regulator must be enabled (done into HAL_ADC_Init()). - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc) -{ - uint32_t tickstart; - __IO uint32_t wait_loop_index = 0UL; - - /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ - /* enabling phase not yet completed: flag ADC ready not yet set). */ - /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ - /* causes: ADC clock not running, ...). */ - if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - { - /* Check if conditions to enable the ADC are fulfilled */ - if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - - /* Enable the ADC peripheral */ - LL_ADC_Enable(hadc->Instance); - - if ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) - != 0UL) - { - /* Delay for temperature sensor buffer stabilization time */ - /* Wait loop initialization and execution */ - /* Note: Variable divided by 2 to compensate partially */ - /* CPU processing cycles, scaling in us split to not */ - /* exceed 32 bits register capacity and handle low frequency. */ - wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US / 10UL) - * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); - while (wait_loop_index != 0UL) - { - wait_loop_index--; - } - } - - /* If low power mode AutoPowerOff is enabled, power-on/off phases are */ - /* performed automatically by hardware and flag ADC ready is not set. */ - if (hadc->Init.LowPowerAutoPowerOff != ENABLE) - { - /* Wait for ADC effectively enabled */ - tickstart = HAL_GetTick(); - - while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL) - { - /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit - has been cleared (after a calibration), ADEN bit is reset by the - calibration logic. - The workaround is to continue setting ADEN until ADRDY is becomes 1. - Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this - 4 ADC clock cycle duration */ - /* Note: Test of ADC enabled required due to hardware constraint to */ - /* not enable ADC if already enabled. */ - if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - { - LL_ADC_Enable(hadc->Instance); - } - - if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - } - } - } - - /* Return HAL status */ - return HAL_OK; -} - -/** - * @brief Disable the selected ADC. - * @note Prerequisite condition to use this function: ADC conversions must be - * stopped. - * @param hadc ADC handle - * @retval HAL status. - */ -HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc) -{ - uint32_t tickstart; - const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance); - - /* Verification if ADC is not already disabled: */ - /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ - /* disabled. */ - if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) - && (tmp_adc_is_disable_on_going == 0UL) - ) - { - /* Check if conditions to disable the ADC are fulfilled */ - if ((hadc->Instance->CR & (ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN) - { - /* Disable the ADC peripheral */ - LL_ADC_Disable(hadc->Instance); - __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); - } - else - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - - /* Wait for ADC effectively disabled */ - /* Get tick count */ - tickstart = HAL_GetTick(); - - while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL) - { - if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - } - } - - /* Return HAL status */ - return HAL_OK; -} - -/** - * @brief DMA transfer complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Update state machine on conversion status if not in error state */ - if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL) - { - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); - - /* Determine whether any further conversion upcoming on group regular */ - /* by external trigger, continuous mode or scan sequence on going */ - /* to disable interruption. */ - if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL) - && (hadc->Init.ContinuousConvMode == DISABLE) - ) - { - /* If End of Sequence is reached, disable interrupts */ - if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS)) - { - /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ - /* ADSTART==0 (no conversion on going) */ - if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL) - { - /* Disable ADC end of single conversion interrupt on group regular */ - /* Note: Overrun interrupt was enabled with EOC interrupt in */ - /* HAL_Start_IT(), but is not disabled here because can be used */ - /* by overrun IRQ process below. */ - __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_READY); - } - else - { - /* Change ADC state to error state */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - } - } - } - - /* Conversion complete callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ConvCpltCallback(hadc); -#else - HAL_ADC_ConvCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - } - else /* DMA and-or internal error occurred */ - { - if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL) - { - /* Call HAL ADC Error Callback function */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ErrorCallback(hadc); -#else - HAL_ADC_ErrorCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ - } - else - { - /* Call ADC DMA error callback */ - hadc->DMA_Handle->XferErrorCallback(hdma); - } - } -} - -/** - * @brief DMA half transfer complete callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Half conversion callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ConvHalfCpltCallback(hadc); -#else - HAL_ADC_ConvHalfCpltCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -} - -/** - * @brief DMA error callback. - * @param hdma pointer to DMA handle. - * @retval None - */ -static void ADC_DMAError(DMA_HandleTypeDef *hdma) -{ - /* Retrieve ADC handle corresponding to current DMA handle */ - ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - - /* Set ADC state */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); - - /* Set ADC error code to DMA error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); - - /* Error callback */ -#if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) - hadc->ErrorCallback(hadc); -#else - HAL_ADC_ErrorCallback(hadc); -#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ -} - -/** - * @} - */ - -#endif /* HAL_ADC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ - diff --git a/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c b/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c deleted file mode 100644 index dfb24ae..0000000 --- a/Drivers/STM32C0xx_HAL_Driver/Src/stm32c0xx_hal_adc_ex.c +++ /dev/null @@ -1,417 +0,0 @@ -/** - ****************************************************************************** - * @file stm32c0xx_hal_adc_ex.c - * @author MCD Application Team - * @brief This file provides firmware functions to manage the following - * functionalities of the Analog to Digital Converter (ADC) - * peripheral: - * + Operation functions - * ++ Calibration - * +++ ADC automatic self-calibration - * +++ Calibration factors get or set - * Other functions (generic functions) are available in file - * "stm32c0xx_hal_adc.c". - * - ****************************************************************************** - * @attention - * - * Copyright (c) 2022 STMicroelectronics. - * All rights reserved. - * - * This software is licensed under terms that can be found in the LICENSE file - * in the root directory of this software component. - * If no LICENSE file comes with this software, it is provided AS-IS. - * - ****************************************************************************** - @verbatim - [..] - (@) Sections "ADC peripheral features" and "How to use this driver" are - available in file of generic functions "stm32c0xx_hal_adc.c". - [..] - @endverbatim - ****************************************************************************** - */ - -/* Includes ------------------------------------------------------------------*/ -#include "stm32c0xx_hal.h" - -/** @addtogroup STM32C0xx_HAL_Driver - * @{ - */ - -/** @defgroup ADCEx ADCEx - * @brief ADC Extended HAL module driver - * @{ - */ - -#ifdef HAL_ADC_MODULE_ENABLED - -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ - -/** @defgroup ADCEx_Private_Constants ADC Extended Private Constants - * @{ - */ - -/* Fixed timeout value for ADC calibration. */ -/* Values defined to be higher than worst cases: maximum ratio between ADC */ -/* and CPU clock frequencies. */ -/* Example of profile low frequency : ADC frequency at 31.25kHz (ADC clock */ -/* source 8MHz, ADC clock prescaler 256), CPU frequency 48MHz. */ -/* Calibration time max = 116 / fADC (refer to datasheet) */ -/* = 178 176 CPU cycles */ -#define ADC_CALIBRATION_TIMEOUT (178176UL) /*!< ADC calibration time-out value (unit: CPU cycles) */ -#define ADC_DISABLE_TIMEOUT (2UL) - -/** - * @} - */ - -/* Private macro -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup ADCEx_Exported_Functions ADC Extended Exported Functions - * @{ - */ - -/** @defgroup ADCEx_Exported_Functions_Group1 Extended Input and Output operation functions - * @brief Extended IO operation functions - * -@verbatim - =============================================================================== - ##### IO operation functions ##### - =============================================================================== - [..] This section provides functions allowing to: - - (+) Perform the ADC self-calibration. - (+) Get calibration factors. - (+) Set calibration factors. - -@endverbatim - * @{ - */ - -/** - * @brief Perform an ADC automatic self-calibration - * Calibration prerequisite: ADC must be disabled (execute this - * function before HAL_ADC_Start() or after HAL_ADC_Stop() ). - * @note Calibration factor can be read after calibration, using function - * HAL_ADC_GetValue() (value on 7 bits: from DR[6;0]). - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - __IO uint32_t wait_loop_index = 0UL; - uint32_t backup_setting_cfgr1; - uint32_t calibration_index; - uint32_t calibration_factor_accumulated = 0; - uint32_t tickstart; - uint32_t adc_clk_async_presc; - __IO uint32_t delay_cpu_cycles; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Calibration prerequisite: ADC must be disabled. */ - - /* Disable the ADC (if not already disabled) */ - tmp_hal_status = ADC_Disable(hadc); - - /* Check if ADC is effectively disabled */ - if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - { - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_REG_BUSY, - HAL_ADC_STATE_BUSY_INTERNAL); - - /* Manage settings impacting calibration */ - /* - Disable ADC mode auto power-off */ - /* - Disable ADC DMA transfer request during calibration */ - /* Note: Specificity of this STM32 series: Calibration factor is */ - /* available in data register and also transferred by DMA. */ - /* To not insert ADC calibration factor among ADC conversion data */ - /* in array variable, DMA transfer must be disabled during */ - /* calibration. */ - backup_setting_cfgr1 = READ_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF); - CLEAR_BIT(hadc->Instance->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG | ADC_CFGR1_AUTOFF); - - /* ADC calibration procedure */ - /* Note: Perform an averaging of 8 calibrations for optimized accuracy */ - for (calibration_index = 0UL; calibration_index < 8UL; calibration_index++) - { - /* Start ADC calibration */ - LL_ADC_StartCalibration(hadc->Instance); - - /* Wait for calibration completion */ - while (LL_ADC_IsCalibrationOnGoing(hadc->Instance) != 0UL) - { - wait_loop_index++; - if (wait_loop_index >= ADC_CALIBRATION_TIMEOUT) - { - /* Update ADC state machine to error */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_ERROR_INTERNAL); - - __HAL_UNLOCK(hadc); - - return HAL_ERROR; - } - } - - calibration_factor_accumulated += LL_ADC_GetCalibrationFactor(hadc->Instance); - } - /* Compute average */ - calibration_factor_accumulated /= calibration_index; - /* Apply calibration factor (requires ADC enable and disable process) */ - LL_ADC_Enable(hadc->Instance); - - /* Case of ADC clocked at low frequency: Delay required between ADC enable and disable actions */ - if (LL_ADC_GetClock(hadc->Instance) == LL_ADC_CLOCK_ASYNC) - { - adc_clk_async_presc = LL_ADC_GetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance)); - - if (adc_clk_async_presc >= LL_ADC_CLOCK_ASYNC_DIV16) - { - /* Delay loop initialization and execution */ - /* Delay depends on ADC clock prescaler: Compute ADC clock asynchronous prescaler to decimal format */ - delay_cpu_cycles = (1UL << ((adc_clk_async_presc >> ADC_CCR_PRESC_Pos) - 3UL)); - /* Divide variable by 2 to compensate partially CPU processing cycles */ - delay_cpu_cycles >>= 1UL; - - while (delay_cpu_cycles != 0UL) - { - delay_cpu_cycles--; - } - } - } - - LL_ADC_SetCalibrationFactor(hadc->Instance, calibration_factor_accumulated); - LL_ADC_Disable(hadc->Instance); - - /* Wait for ADC effectively disabled before changing configuration */ - /* Get tick count */ - tickstart = HAL_GetTick(); - - while (LL_ADC_IsEnabled(hadc->Instance) != 0UL) - { - if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) - { - /* New check to avoid false timeout detection in case of preemption */ - if (LL_ADC_IsEnabled(hadc->Instance) != 0UL) - { - /* Update ADC state machine to error */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Set ADC error code to ADC peripheral internal error */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - return HAL_ERROR; - } - } - } - - /* Restore configuration after calibration */ - SET_BIT(hadc->Instance->CFGR1, backup_setting_cfgr1); - - /* Set ADC state */ - ADC_STATE_CLR_SET(hadc->State, - HAL_ADC_STATE_BUSY_INTERNAL, - HAL_ADC_STATE_READY); - } - else - { - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); - - /* Note: No need to update variable "tmp_hal_status" here: already set */ - /* to state "HAL_ERROR" by function disabling the ADC. */ - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Get the calibration factor. - * @param hadc ADC handle. - * @retval Calibration value. - */ -uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc) -{ - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Return the selected ADC calibration value */ - return ((hadc->Instance->CALFACT) & 0x0000007FU); -} - -/** - * @brief Set the calibration factor to overwrite automatic conversion result. - * ADC must be enabled and no conversion is ongoing. - * @param hadc ADC handle - * @param CalibrationFactor Calibration factor (coded on 7 bits maximum) - * @retval HAL state - */ -HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor) -{ - HAL_StatusTypeDef tmp_hal_status = HAL_OK; - uint32_t tmp_adc_is_conversion_on_going_regular; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - assert_param(IS_ADC_CALFACT(CalibrationFactor)); - - /* Process locked */ - __HAL_LOCK(hadc); - - /* Verification of hardware constraints before modifying the calibration */ - /* factors register: ADC must be enabled, no conversion on going. */ - tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance); - - if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL) - && (tmp_adc_is_conversion_on_going_regular == 0UL) - ) - { - hadc->Instance->CALFACT &= ~ADC_CALFACT_CALFACT; - hadc->Instance->CALFACT |= CalibrationFactor; - } - else - { - /* Update ADC state machine */ - SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); - /* Update ADC error code */ - SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); - - /* Update ADC state machine to error */ - tmp_hal_status = HAL_ERROR; - } - - /* Process unlocked */ - __HAL_UNLOCK(hadc); - - /* Return function status */ - return tmp_hal_status; -} - -/** - * @brief Analog watchdog 2 callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADCEx_LevelOutOfWindow2Callback must be implemented in the user file. - */ -} - -/** - * @brief Analog watchdog 3 callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADCEx_LevelOutOfWindow3Callback must be implemented in the user file. - */ -} - - -/** - * @brief End Of Sampling callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADCEx_EndOfSamplingCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADCEx_EndOfSamplingCallback must be implemented in the user file. - */ -} - -/** - * @brief ADC channel configuration ready callback in non-blocking mode. - * @param hadc ADC handle - * @retval None - */ -__weak void HAL_ADCEx_ChannelConfigReadyCallback(ADC_HandleTypeDef *hadc) -{ - /* Prevent unused argument(s) compilation warning */ - UNUSED(hadc); - - /* NOTE : This function should not be modified. When the callback is needed, - function HAL_ADCEx_ChannelConfigReadyCallback must be implemented in the user file. - */ -} - -/** - * @} - */ - -/** - * @brief Disable ADC voltage regulator. - * @note Disabling voltage regulator allows to save power. This operation can - * be carried out only when ADC is disabled. - * @note To enable again the voltage regulator, the user is expected to - * resort to HAL_ADC_Init() API. - * @param hadc ADC handle - * @retval HAL status - */ -HAL_StatusTypeDef HAL_ADCEx_DisableVoltageRegulator(ADC_HandleTypeDef *hadc) -{ - HAL_StatusTypeDef tmp_hal_status; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); - - /* Setting of this feature is conditioned to ADC state: ADC must be ADC disabled */ - if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) - { - LL_ADC_DisableInternalRegulator(hadc->Instance); - tmp_hal_status = HAL_OK; - } - else - { - tmp_hal_status = HAL_ERROR; - } - - return tmp_hal_status; -} - -/** - * @} - */ - -/** - * @} - */ - -#endif /* HAL_ADC_MODULE_ENABLED */ -/** - * @} - */ - -/** - * @} - */ diff --git a/rey_master.ioc b/rey_master.ioc index a99e29c..607238d 100644 --- a/rey_master.ioc +++ b/rey_master.ioc @@ -1,8 +1,4 @@ #MicroXplorer Configuration settings - do not modify -ADC1.IPParameters=NbrOfConversionFlag,master,SelectedChannel -ADC1.NbrOfConversionFlag=0 -ADC1.SelectedChannel=ADC_CHANNEL_8 -ADC1.master=1 CAD.formats= CAD.pinconfig= CAD.provider= @@ -11,30 +7,28 @@ GPIO.groupedBy=Group By Peripherals KeepUserPlacement=false Mcu.CPN=STM32C011F6P6 Mcu.Family=STM32C0 -Mcu.IP0=ADC1 -Mcu.IP1=CORTEX_M0+ -Mcu.IP2=DEBUG -Mcu.IP3=NVIC -Mcu.IP4=RCC -Mcu.IP5=SYS -Mcu.IPNb=6 +Mcu.IP0=CORTEX_M0+ +Mcu.IP1=DEBUG +Mcu.IP2=NVIC +Mcu.IP3=RCC +Mcu.IP4=SYS +Mcu.IPNb=5 Mcu.Name=STM32C011F(4-6)Px Mcu.Package=TSSOP20 Mcu.Pin0=PA0 Mcu.Pin1=PA1 -Mcu.Pin10=PA12 [PA10] -Mcu.Pin11=PA13 -Mcu.Pin12=PA14-BOOT0 -Mcu.Pin13=VP_SYS_VS_Systick +Mcu.Pin10=PA13 +Mcu.Pin11=PA14-BOOT0 +Mcu.Pin12=VP_SYS_VS_Systick Mcu.Pin2=PA2 Mcu.Pin3=PA3 Mcu.Pin4=PA4 Mcu.Pin5=PA5 Mcu.Pin6=PA6 Mcu.Pin7=PA7 -Mcu.Pin8=PA8 -Mcu.Pin9=PA11 [PA9] -Mcu.PinsNb=14 +Mcu.Pin8=PA11 [PA9] +Mcu.Pin9=PA12 [PA10] +Mcu.PinsNb=13 Mcu.ThirdPartyNb=0 Mcu.UserConstants= Mcu.UserName=STM32C011F6Px @@ -93,9 +87,6 @@ PA7.GPIOParameters=GPIO_Label PA7.GPIO_Label=Amber_LED_OUT PA7.Locked=true PA7.Signal=GPIO_Output -PA8.Locked=true -PA8.Mode=IN8 -PA8.Signal=ADC1_IN8 PinOutPanel.RotationAngle=0 ProjectManager.AskForMigrate=true ProjectManager.BackupPrevious=false @@ -127,7 +118,7 @@ ProjectManager.ToolChainLocation= ProjectManager.UAScriptAfterPath= ProjectManager.UAScriptBeforePath= ProjectManager.UnderRoot=true -ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,0-MX_CORTEX_M0+_Init-CORTEX_M0+-false-HAL-true +ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ADC1_Init-ADC1-false-HAL-true,0-MX_CORTEX_M0+_Init-CORTEX_M0+-false-HAL-true RCC.ADCFreq_Value=12000000 RCC.AHBFreq_Value=12000000 RCC.APBFreq_Value=12000000